The ADS1000-Q1 communicates through an inter-integrated circuit (I²C) interface. The I²C interface is a two-wire, open-drain interface supporting multiple devices and controllers on a single bus. Devices on the I²C bus only drive the bus lines low, by connecting the lines to ground; the devices never drive the bus lines high. Instead, the bus wires are pulled high by pullup resistors, so the bus wires are high when no device is driving them low. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Communication on the I²C bus always takes place between two devices, one acting as the controller and the other acting as the target. Both controllers and targets can read and write, but targets can only do so under the direction of the controller. Some I²C devices can act as controllers or targets, but the ADS1000-Q1 can only act as a target device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data, SCL provides the clock. All data are transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the bit level while SCL is low (a low on SDA indicates the bit is 0b; a high indicates the bit is 1b). When the SDA line has settled, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a controller reads from a target, the target drives the data line; when a controller sends to a target, the controller drives the data line. The controller always drives the clock line. The ADS1000-Q1 never drives SCL, because the device cannot act as a controller. On the ADS1000-Q1, SCL is an input only.

Most of the time the bus is idle, no communication takes place, and both lines are high. When communication takes place, the bus is active. Only controller devices can start a communication. These devices initiate a communication by causing a start condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes state while the clock line is high, the data line is either a start condition or a stop condition. A start condition is when the clock line is high and the data line goes from high to low. A stop condition is when the clock line is high and the data line goes from low to high.

After the controller issues a start condition, the controller sends a byte that indicates which target device to communicate to. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address to which the device responds. (Targets can also have 10-bit addresses; see the I²C specification for details.) The controller sends an address in the address byte, together with a bit that indicates whether a read from or write to the target device is needed.

Every byte transmitted on the I²C bus, whether address or data, is acknowledged with an acknowledge bit. When a controller finishes sending a byte, eight data bits, to a target, the controller stops driving SDA and waits for the target to acknowledge the byte. The target acknowledges the byte by pulling SDA low. The controller then sends a clock pulse to clock the acknowledge bit. Similarly, when a controller has finished reading a byte, the controller pulls SDA low to acknowledge to the target that the byte has been read. The controller then sends a clock pulse to clock the bit. (Remember that the controller always drives the clock line.)

A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not present on the bus, and the controller attempts to address the device, the controller receives a not-acknowledge because no device is present at that address to pull the line low.

When a controller has finished communicating with a target, the controller can issue a stop condition. When a stop condition is issued, the bus becomes idle again. A controller can also issue another start condition. When a start condition is issued while the bus is active, this condition is called a repeated start condition.

Figure 6-1 illustrates a timing diagram for an ADS1000-Q1 I²C transaction. The Timing Requirements table gives the parameters for this diagram.