ZHCSHA5E july   2010  – july 2023 ADS1013-Q1 , ADS1014-Q1 , ADS1015-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6.   Device Comparison Table
  7. 5 Pin Configuration and Functions
  8. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: I2C
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Multiplexer
      2. 7.3.2 Analog Inputs
      3. 7.3.3 Full-Scale Range (FSR) and LSB Size
      4. 7.3.4 Voltage Reference
      5. 7.3.5 Oscillator
      6. 7.3.6 Output Data Rate and Conversion Time
      7. 7.3.7 Digital Comparator (ADS1014-Q1 and ADS1015-Q1 Only)
      8. 7.3.8 Conversion Ready Pin (ADS1014-Q1 and ADS1015-Q1 Only)
      9. 7.3.9 SMbus Alert Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset and Power-Up
      2. 7.4.2 Operating Modes
        1. 7.4.2.1 Single-Shot Mode
        2. 7.4.2.2 Continuous-Conversion Mode
      3. 7.4.3 Duty Cycling For Low Power
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 I2C Address Selection
        2. 7.5.1.2 I2C General Call
        3. 7.5.1.3 I2C Speed Modes
      2. 7.5.2 Target Mode Operations
        1. 7.5.2.1 Receive Mode
        2. 7.5.2.2 Transmit Mode
      3. 7.5.3 Writing To and Reading From the Registers
      4. 7.5.4 Data Format
    6. 7.6 Register Map
      1. 7.6.1 Address Pointer Register (address = N/A) [reset = N/A]
      2. 7.6.2 Conversion Register (P[1:0] = 00b) [reset = 0000h]
      3. 7.6.3 Config Register (P[1:0] = 01b) [reset = 8583h]
      4. 7.6.4 Lo_thresh (P[1:0] = 10b) [reset = 8000h] and Hi_thresh (P[1:0] = 11b) [reset = 7FFFh] Registers
  10. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Connections
      2. 8.1.2 Single-Ended Inputs
      3. 8.1.3 Input Protection
      4. 8.1.4 Unused Inputs and Outputs
      5. 8.1.5 Analog Input Filtering
      6. 8.1.6 Connecting Multiple Devices
      7. 8.1.7 Quick-Start Guide
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Considerations
        2. 8.2.2.2 Operational Amplifier Considerations
        3. 8.2.2.3 ADC Input Common-Mode Considerations
        4. 8.2.2.4 Resistor (R1, R2, R3, R4) Considerations
        5. 8.2.2.5 Noise and Input Impedance Considerations
        6. 8.2.2.6 First-Order RC Filter Considerations
        7. 8.2.2.7 Circuit Implementation
        8. 8.2.2.8 Results Summary
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power-Supply Sequencing
      2. 8.3.2 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  12. 10Mechanical, Packaging, and Orderable Information

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8.1.7 Quick-Start Guide

This section provides a brief example of ADS101x-Q1 communications. Hardware for this design includes: one ADS101x-Q1 configured with an I2C address of 1001000b; a microcontroller with an I2C interface; discrete components such as resistors, capacitors, and serial connectors; and a 2-V to 5-V power supply. Figure 8-5 shows the basic hardware configuration.

The ADS101x-Q1 communicate with the controller (microcontroller) through an I2C interface. The controller provides a clock signal on the SCL pin and data are transferred using the SDA pin. The ADS101x-Q1 never drive the SCL pin. For information on programming and debugging the microcontroller being used, see the device-specific product data sheet.

The first byte sent by the controller is the ADS101x-Q1 address, followed by the R/W bit that instructs the ADS101x-Q1 to listen for a subsequent byte. The second byte is the Address Pointer register byte. The third and fourth bytes sent from the controller are written to the register indicated in register address pointer bits P[1:0]. See Figure 7-9 and Figure 7-10 for read and write operation timing diagrams, respectively. All read and write transactions with the ADS101x-Q1 must be preceded by a START condition, and followed by a STOP condition.

For example, to write to the configuration register to set the ADS101x-Q1 to continuous-conversion mode and then read the conversion result, send the following bytes in this order:

  1. Write to Config register:
    • First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
    • Second byte: 00000001b (points to Config register)
    • Third byte: 10000100b (MSB of the Config register to be written)
    • Fourth byte: 10000011b (LSB of the Config register to be written)
  2. Write to Address Pointer register:
    • First byte: 10010000b (first 7-bit I2C address followed by a low R/W bit)
    • Second byte: 00000000b (points to Conversion register)
  3. Read Conversion register:
    • First byte: 10010001b (first 7-bit I2C address followed by a high R/W bit)
    • Second byte: the ADS101x-Q1 responds with the MSB of the Conversion register
    • Third byte: the ADS101x-Q1 responds with the LSB of the Conversion register
GUID-0772CC25-A603-4DB3-99A9-E76E5D643B37-low.svgFigure 8-5 Basic Hardware Configuration
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