The low-latency filter is a cascaded-integrator-comb (CIC) topology that minimizes the delay (latency) as the conversion data propagates through the filter. The CIC filter is otherwise known as a sinc filter because of the characteristic sinx/x (sinc) frequency response. The latency time is shorter compared to the wideband filter, making the filter suitable for fast acquisition of dc signals. The device offers the choice of four sinc filter configurations: sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1 to provide trade-offs of acquisition time, noise performance, and line-cycle rejection.

Latency is defined as the time from synchronization to the falling edge of DRDY, at which time, fully settled data are available. Data do not need to be discarded because unsettled data are suppressed by the ADC. Detailed latency data for each sinc filter mode are given in Table 8-4 through Table 8-7.

If the input is changed without synchronization, then the next conversion data are partially settled. The number of conversions required for fully settled data in this case is found by rounding the latency time value to the next whole number of conversion periods.

Equation 14 is the general expression of the sinc-filter frequency response. For single-stage sinc filter options (for example, the single-stage sinc3 or sinc4 filter), the second stage is not used.

where:

• f = Signal frequency
• A = Stage 1 OSR, B = Stage 2 OSR
• f_MOD = f_CLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode)
• n = Order of the stage 1 filter (3 or 4)