米6体育平台手机版

ZHCSKD9 October 2019 ADS1235-Q1

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RHM|32
- MPQF152B

散热焊盘机械数据 (封装 | 引脚)

RHM|32
- QFND568

订购信息

zhcskd9_oa

6.5 Electrical Characteristics

minimum and maximum specifications apply from T_A= –40°C to +125°C; typical specifications are at T_A = 25°C; all specifications at AVDD = 5 V, AVSS = 0 V, DVDD = 3.3 V, V_REF = 5 V, f_CLK = 7.3728 MHz, PGA mode, gain = 1, and data rate = 20 SPS (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Absolute input current	PGA mode, V_(AINx) = 2.5 V		4	12	nA
	Absolute input current	PGA bypass		200		nA
	Absolute input current drift			0.01		nA/°C
	Differential input current	PGA mode, V_IN = 39 mV		±0.1		nA
		PGA mode, V_IN = 2.5 V	–8	±1	8
		PGA and chop modes, V_IN = 2.5 V⁽⁵⁾		±5
		PGA bypass, V_IN = 2.5 V		±40
	Differential input current drift			0.05		nA/°C
	Differential input impedance	PGA mode		1		GΩ
	Differential input impedance	PGA bypass		50		MΩ
	Crosstalk			0.1		µV/V
PGA
	Gain settings			1, 64, 128		V/V
	Antialias filter frequency	C_{CAPP, CAPN} = 4.7 nF		60		kHz
	Output voltage monitor	Low threshold		AVSS + 0.2		V
	Output voltage monitor	High threshold		AVDD – 0.2		V
PERFORMANCE
	Resolution	No missing codes	24			Bits
	Equivalent input noise density	Gain = 64 and 128		8		nV/√Hz
DR	Data rate		2.5		7200	SPS
	Noise performance		See Table 1
INL	Integral non-linearity	Gain = 1, 64 and 128	–10	±2	10	ppm_FSR
V_OS	Offset voltage	T_A = 25°C, gain = 1	–355	±50	355	µV
		T_A = 25°C, gain = 64 and 128	–10	±1.5	10
		T_A = 25°C, gain = 1, chop mode	–0.6	±0.2	0.6
		T_A = 25°C, gain = 64 and 128, chop mode	–0.06	±0.005	0.06
		After calibration	On the level of noise
	Offset voltage drift	Gain = 1		150	350	nV/°C
		Gain = 64 and 128		15	75
		Gain = 1, 64, and 128, chop mode		1	5
GE	Gain error	T_A = 25°C	–0.6%	±0.05%	0.6%
GE	Gain error	After calibration	on the level of noise
	Gain drift			0.5	4	ppm/°C
NMRR	Normal-mode rejection ratio⁽¹⁾		See Table 5
CMRR	Common-mode rejection ratio⁽²⁾	Data rate = 20 SPS		130		dB
CMRR	Common-mode rejection ratio⁽²⁾	Data rate = 400 SPS	105	115		dB
PSRR	Power-supply rejection ratio⁽³⁾	AVDD and AVSS	85	100		dB
PSRR	Power-supply rejection ratio⁽³⁾	DVDD	95	120		dB
INTERNAL OSCILLATOR
f_CLK	Frequency			7.3728		MHz
	Accuracy		–2%	±0.5%	2%
VOLTAGE REFERENCE INPUTS
	Reference input current			500		nA
	Input current vs voltage			100		nA/V
	Input current drift			0.1		nA//V/°C
	Input impedance	Differential		5		MΩ
	Low voltage monitor	Threshold low		0.4	0.6	V
TEMPERATURE SENSOR
	Sensor voltage	T_A = 25°C		122.4		mV
	Temperature coefficient			420		µV/°C
GENERAL-PURPOSE INPUTS/OUTPUTS (GPIOs)⁽⁶⁾
V_OL	Low-level output voltage	I_OL = –1 mA			0.2 · AVDD	V
V_OH	High-level output voltage	I_OH = 1 mA	0.8 · AVDD			V
V_IL	Low-level input voltage				0.3 · AVDD	V
V_IH	High-level input voltage		0.7 · AVDD			V
	Input hysteresis			0.5		V
DIGITAL INPUTS/OUTPUTS (Other Than GPIOs)
V_OL	Low-level output voltage	I_OL = –1 mA			0.2 · DVDD	V
V_OL	Low-level output voltage	I_OL = –8 mA		0.2 · DVDD		V
V_OH	High-level output voltage	I_OH = 1 mA	0.8 · DVDD			V
V_OH	High-level output voltage	I_OH = 8 mA		0.75 · DVDD		V
V_IL	Low-level input voltage				0.3 · DVDD	V
V_IH	High-level input voltage		0.7 · DVDD			V
	Input hysteresis			0.1		V
	Input leakage	V_IH or V_IL	–10		10	µA
POWER SUPPLY
I_AVDD I_AVSS	Analog supply current	PGA bypass		2.7	4.5	mA
		PGA mode, gain = 64 and 128		4.3	6.5	mA
		Power-down mode		2	8	µA
I_DVDD	Digital supply current			0.4	0.7	mA
I_DVDD	Digital supply current	Power-down mode⁽⁴⁾		30	75	µA
P_D	Power dissipation	PGA mode, gain = 64 and 128		23	35	mW
P_D	Power dissipation	Power-down mode		0.1	0.3	mW

(1) Normal-mode rejection ratio performance depends on the digital filter configuration.

(2) Common-mode rejection ratio is specified at f_IN= 60 Hz.

(3) Power-supply rejection ratio specified at dc.

(4) CLKIN input stopped.

(5) Chop-mode input current scales with data rate. See Figure 27 for chop mode input current at 20 SPS and 1200 SPS.

(6) GPIO voltage with respect to AVSS.