9.3.1 Input Multiplexer

Figure 23 shows a simplified diagram of the input multiplexer. Select any pin as the positive input (AIN_P) and any pin as the negative input (AIN_N). Pin selection is controlled by the MUX register.

Figure 23. Simplified Diagram of the Input Multiplexer

The ADS1257 offers four analog inputs that can be configured as two independent differential inputs, three single-ended inputs, or a combination of differential and single-ended inputs.

In general, there are no restrictions on input-pin selection. However, follow these recommendations for optimal performance:

1. Preferably, use adjacent inputs for differential measurements. For example, use AIN0 and AIN1.
2. Leave any unused analog inputs floating, or connect them to AVDD in order to minimize the input-pin leakage current.

ESD diodes protect the analog inputs. To keep these diodes from turning on, voltages on the input pins must not go below AGND by more than 100 mV, and likewise, must not exceed AVDD by more than 100 mV: −100 mV < (V_(AINx)) < AVDD + 100 mV.

9.3.2 Analog Input Buffer

To increase the input impedance presented by the ADS1257, enable the low-drift, chopper-stabilized buffer using the BUFEN bit in the STATUS register. As shown in Figure 24, the input impedance with the buffer enabled is modeled by a resistor. Table 5 lists the values of Zeff for the different data-rate settings. The input impedance scales inversely with the frequency of CLKIN. For example, if f_(CLKIN) is reduced by half to 3.84 MHz, Zeff for a data-rate setting of 50 SPS (actual data rate of 25 SPS) doubles from 80 MΩ to 160 MΩ.s

Figure 24. Effective Impedance with Buffer On

9.3.3 Programmable Gain Amplifier (PGA)

The ADS1257 is a very high resolution converter. To further complement converter performance, the low-noise PGA increases the ADC resolution when measuring smaller input signals. For the best resolution, set the PGA to the highest possible gain setting. The gain setting depends on the largest input signal to be measured. The ADS1257 full-scale input voltage equals ±2 · V_REF / Gain. Table 6 shows the full-scale input voltage for the different PGA gain settings for V_REF = 2.5 V. For example, if the largest signal to be measured is 1.0 V, the optimum PGA gain setting is 4 V/V, producing a full-scale input voltage of 4 V with no ADC overrange.

The PGA is controlled by the ADCON register. Recalibrate the ADC after changing the PGA gain setting. The time required for self-calibration depends on the PGA gain setting; see the Calibration section for more details. The analog current and input impedance (when the buffer is disabled) vary as a function of the PGA gain setting.

9.3.4 Modulator Input Circuitry

The ADS1257 modulator measures the input signal using internal capacitors that are continuously charged and discharged. Figure 25 shows a simplified schematic of the ADS1257 input circuitry with the input buffer disabled. The on and off timing of the S1 and S2 switches are shown in Figure 26. The S1 switch closes during the input sampling phase. With S1 closed, C_A1 charges to V_(AINP), C_A2 charges to V_(AINN), and C_B charges to
(V_(AINP) – V_(AINN)). For the discharge phase, S1 opens first and then S2 closes. C_A1 and C_A2 discharge to approximately AVDD / 2 and C_B discharges to 0 V. This two-phase sample and discharge cycle repeats with a period of t_SAMPLE. This time is a function of the PGA gain setting as shown in Table 7 along with the values of capacitors C_A1 = C_A2 = C_A and C_B.

Figure 25. Simplified Input Structure with Buffer Off

Figure 26. S1 and S2 Switch Timing for Figure 25

The charging of the input capacitors draws a transient current from the sensor driving the ADS1257 inputs. The average value of this current is used to calculate an effective impedance Zeff, where Zeff = V_IN / I_AVERAGE. Figure 27 shows the input circuitry with the capacitors and switches of Figure 25 replaced by their effective impedances. These impedances scale inversely with the CLKIN frequency. For example, if f_(CLKIN) is reduced by a factor of two, the impedances double. The impedance also changes with the PGA gain setting. Table 8 lists the effective impedances with the buffer off for f_(CLKIN) = 7.68 MHz.

Figure 27. Analog Input Effective Impedances with Buffer Off

9.3.5 Voltage Reference Inputs (REFP, REFN)

The ADC requires a reference voltage for operation. The reference voltage for the ADS1257 is the differential voltage between REFP and REFN: V_REF = V_(REFP) − V_(REFN). The reference inputs use a structure similar to that of the analog inputs with the circuitry on the reference inputs of Figure 28. The load presented by the switched capacitor is modeled with an effective impedance (Zeff) of 18.5 kΩ for f_(CLKIN) = 7.68 MHz. The temperature coefficient of the effective impedance of the voltage reference inputs is approximately 35 ppm/°C.

1. f_(CLKIN) = 7.68 MHz

Figure 28. Simplified Reference Input Circuitry

ESD diodes protect the reference inputs. To keep these diodes from turning on, the voltages on the reference pins must not go below AGND by more than 100 mV, and must not exceed AVDD by 100 mV:

AGND − 100 mV < (V_(REFP) or V_(REFN)) < AVDD + 100 mV

During self gain calibration, all the switches in the input multiplexer are opened, REFN is internally connected to AIN_N, and REFP is connected to AIN_P. The input buffer can be disabled or enabled during calibration. When the buffer is disabled, the reference pins drive the circuitry shown in Figure 25 during self gain calibration, resulting in increased loading. To prevent this additional loading from introducing gain errors, the circuitry driving the reference pins must have adequate drive capability. When the buffer is enabled, the loading on the reference pins is much less. However, the buffer limits the allowable voltage range on REFP and REFN during self- or self gain calibration because the reference pins must remain within the specified input range of the buffer in order to establish proper gain calibration.

A high-quality reference voltage capable of driving the switched capacitor load presented by the ADS1257 is essential for achieving the best performance. Noise and drift on the reference degrade overall system performance. Take special care with the circuitry generating the reference voltages and their layout when operating with low-noise settings (that is, with low data rates) in order to prevent the voltage reference from limiting performance.

See the External Reference section for more details.

9.3.6 Clock Input (CLKIN)

The master clock for the ADS1257 must be applied to the CLKIN pin. Keep the external clock signal clean and free of overshoot. Overshoot and glitches on the clock degrade overall performance. See the Recommended Operating Conditions section for the recommended master clock frequency range. Some of the timing requirements, as well as the output data rate, scale directly with the CLKIN frequency.

9.3.7 Clock Output (D0/CLKOUT)

Use the clock output pin (D0/CLKOUT) to clock another device, such as another ADS1257 or a microcontroller. This clock operates at frequencies of f_(CLKIN), f_(CLKIN) / 2, or f_(CLKIN) / 4 and is configured by setting the CLK[1:0] bits in the ADCON register. If the output clock is enabled while driving an external load, the digital power consumption increases. Standby mode does not affect the clock output status. That is, if standby is enabled, the clock output continues to run during standby mode. If not needed, disable the clock output function by writing to the CLK bits in the ADCON register after power-up or reset.

9.3.8 General-Purpose Digital I/O (D0, D1)

The ADS1257 offers two pins dedicated for general-purpose digital I/Os. All of the digital I/O pins can be individually configured as either inputs or outputs through the IO register. The DIR bits of the IO register define whether each pin is an input or output, and the DIO bits control the status of the pins. Reading back the DIO bits shows the state of the digital I/O pins; that is, if configured as inputs or outputs by the DIR bits. When digital I/O pins are configured as inputs, the DIO bits are used to read the state of these pins. When configured as outputs, writing to the DIO bits sets the output value.

During standby and power-down modes, the GPIOs remain active. If configured as outputs, the GPIOs continue to drive the pins. If configured as inputs, the GPIOs must be driven (not left floating) to prevent excess power dissipation.

After power-up or reset, the D1 pin defaults to an input and the D0/CLKOUT pin defaults to the clock output. The CLK[1:0] bits that control the clock output on D0/CLKOUT are only reset after power-up or RESET pin toggle. If the digital I/O pins are not used, either leave them as inputs tied to ground, or configure them as outputs and leave them floating to avoid excess power dissipation.

9.3.9 Open- and Short-Circuit Sensor Detection

The sensor detect current sources (SDCS) provide a means to verify the integrity of the external sensor connected to the ADS1257. When enabled, the SDCS supply a current (I_SDC) of approximately 0.5 μA, 2 μA, or 10 μA to the sensor through the input multiplexer. The SDCS bits in the ADCON register enable the SDCS and set the value of I_SDC.

When the SDCS are enabled, the ADS1257 automatically turns on the analog input buffer, regardless of the BUFEN bit setting, in order to prevent the input circuitry from loading the SDCS. AIN_P must stay below 3 V to be within the absolute input range of the buffer. To help meet this condition, a 3-V clamp starts sinking current from AIN_P to AGND if AIN_P exceeds 3 V. Note that this clamp is activated only when the SDCS are enabled.

Figure 29 shows a simplified diagram of the ADS1257 input structure with the external sensor modeled as resistance R_SENS between two input pins. When enabled, the SDCS source I_SDC to the input pin connected to AIN_P, and sink I_SDC from the input pin connected to AIN_N. The two 25-Ω series resistors, R_MUX, model the ADS1257 internal multiplexer switch on-resistances. The signal measured with the SDCS enabled equals the total IR drop: I_SDC × (2R_MUX + R_SENS). When the sensor is a direct short (that is, R_SENS = 0 Ω), there is still a small signal measured by the ADS1257 when the SDCS are enabled: I_SDC · 2R_MUX.

NOTE: Arrows indicate switch positions when the SDCS are enabled.

Figure 29. Sensor Detect Circuitry

9.3.10 Digital Filter

The programmable low-pass digital filter receives the modulator output and produces a high-resolution digital output. By adjusting the amount of filtering, tradeoffs can be made between resolution and data rate: filter more for higher resolution, or filter less for higher data rate. The filter is comprised of two sections, a fixed filter followed by a programmable filter. Figure 30 shows the block diagram of the analog modulator and digital filter. Data are supplied to the filter from the analog modulator at a rate of f_(MOD) = f_(CLKIN) / 4. The fixed filter is a fifth-order sinc filter with a decimation value of 64 that outputs data at a rate of f_(CLKIN) / 256. The second stage of the filter is a programmable averager (first-order sinc filter) with the number of averages set by the DRATE register. The data rate is a function of the number of averages (Num_Ave) and is given by Equation 2.

Equation 2.

Figure 30. Block Diagram of the Analog Modulator and Digital Filter

Table 9 shows the averaging and corresponding data rate for each of the 16 valid DRATE register settings when f_(CLKIN) = 7.68 MHz. The data rate scales directly with the CLKIN frequency. For example, reducing f_(CLKIN) from 7.68 MHz to 3.84 MHz reduces the data rate for DR[7:0] = 1111 0000 from 30,000 SPS to 15,000 SPS.

9.3.10.1 Frequency Response

The low-pass digital filter sets the overall frequency response for the ADS1257. The filter response is the product of the responses of the fixed and programmable filter sections, and is given by Equation 3:

Equation 3.

The digital filter attenuates noise on the modulator output, including noise from within the ADS1257 and external noise present on the ADS1257 input signal. Adjusting the filtering by changing the number of averages used in the programmable filter changes the filter bandwidth. With a higher number of averages, bandwidth is reduced, and more noise is attenuated.

The low-pass filter has notches (or zeros) at the data output rate and multiples thereof. At these frequencies, the filter has zero gain. This feature is useful when trying to reject a particular interference signal. For example, to reduce 60-Hz (and harmonic) noise coupling, set the data rate equal to 2.5 SPS, 5 SPS, 10 SPS, 15 SPS, 30 SPS, or 60 SPS. To help illustrate the filter characteristics, Figure 31 and Figure 32 show the responses at the data-rate extremes of 30 kSPS and 2.5 SPS, respectively.

Figure 31. Frequency Response for
Data Rate = 30 kSPS

Figure 32. Frequency Response for
Data Rate = 2.5 SPS

Table 10 summarizes the first-notch frequency and −3-dB bandwidth for the different data-rate settings.

Table 10. First Notch Frequency and
-3-dB Filter Bandwidth⁽¹⁾

DATA RATE (SPS)	FIRST NOTCH (Hz)	-3 dB BANDWIDTH (Hz)
2.5	2.5	1.1
5	5	2.21
10	10	4.42
15	15	6.63
25	25	11.1
30	30	13.3
50	50	22.1
60	60	26.5
100	100	44.2
500	500	221
1000	1000	441
2000	2000	878
3750	3750	1615
7500	7500	3003
15,000	15,000	4807
30,000	30,000	6106

(1) f_(CLKIN) = 7.68 MHz.

The digital filter low-pass characteristic repeats at multiples of the modulator rate of f_(MOD) = f_(CLKIN) / 4. Figure 33 and Figure 34 show the responses plotted out to 7.68 MHz at the data-rate extremes of 30 kSPS and 2.5 SPS. Notice how the responses near dc, 1.92 MHz, 3.84 MHz, 5.76 MHz, and 7.68 MHz are the same. The digital filter attenuates high-frequency noise on the ADS1257 inputs, except for frequencies where the filter response repeats. External filtering is required to remove high-frequency input noise near these pass-band regions. See the Analog Input Filtering section for more details.

Figure 33. Frequency Response Out to 7.68 MHz
for Data Rate = 30 kSPS

Figure 34. Frequency Response Out to 7.68 MHz
for Data Rate = 2.5 SPS

9.4.1 Power-Up

All configuration registers are initialized to default states at power-up. Self-calibration is then performed automatically. For best performance, issue an additional self-calibration with the SELFCAL command or reset the device after the power supplies and voltage reference have settled to their final values.

9.4.2 Reset

Three methods are used to reset the ADS1257: the RESET pin, the RESET command, and a special SCLK reset pattern.

1. Take the RESET pin low to force a reset. Follow the minimum pulse-width timing specification (t₁₆) before taking the RESET pin high again (see Figure 2).
2. Issue the RESET command byte to force a reset (see the RESET section). The RESET command takes effect after all eight bits are shifted into DIN. Afterwards, the reset automatically releases.
3. Reset The ADS1257 using a special pattern on SCLK (see Figure 3). Reset occurs on the falling edge of the last SCLK edge in the pattern. CS must be low to perform the SCLK reset pattern. After performing the operation, the reset automatically releases.

After the device resets, the configuration registers are initialized to their default state, except for the CLK[1:0] bits in the ADCON register that control the D0/CLKOUT pin. The CLK[1:0] bits are only initialized to their default state when reset is performed using the RESET pin. Reset also exits from the read-data continuous mode.

After a reset, the device self-calibrates, regardless of the reset method or the state of the ACAL bit before the reset.

9.4.3 Standby Mode

Standby mode shuts down all of the analog circuitry and most of the digital features. To enter standby mode, issue the STANDBY command. To exit standby mode, issue the WAKEUP command. DRDY stays high after exiting standby mode until valid data are ready.

Use standby mode to perform single-shot conversions; see the Settling Time Using Single-Shot Mode section for more information.

If configured as a clock output, the clock signal on the D0/CLKOUT pin continues to run during standby mode.

9.4.4 Power-Down Mode

Hold the SYNC/PWDN pin low for 20 DRDY cycles to activate power-down mode. During power-down mode, all circuitry is disabled including the clock output.

To exit power-down mode, take the SYNC/PWDN pin high. After exiting from power-down mode, 8192 · t_(CLKIN) cycles are required before conversions begin.

9.4.5 Conversion Control and Synchronization

Device synchronization is available to control the beginning of the analog-to-digital conversion with an external event, and also to improve settling time after a multiplexer change. Two methods are provided to perform synchronization, the SYNC/PWDN pin or the SYNC command:

• Method 1: Take the SYNC/PWDN pin low and then high, in accordance with timing specifications t₁₆ and t_16B. Synchronization occurs when SYNC/PWDN is taken high. No communication is possible on the serial interface while SYNC/PWDN is low. If the SYNC/PWDN pin is held low for 20 DRDY periods, the ADS1257 enters power-down mode.
• Method 2: First, issue the SYNC command. The SYNC command stops the operation of the ADS1257. When ready to synchronize, issue the WAKEUP command. Synchronization occurs on the first rising edge of the master clock after the first SCLK used to shift in the WAKEUP command.

After a synchronization operation, either with the SYNC/PWDN pin or the SYNC command, DRDY stays high until valid data are ready.

The settling time (that is, the time required for a step change on the analog inputs to propagate through the filter) for the different data rates is shown in Table 12 and Figure 35. The following sections highlight the single-cycle settling ability of the filter, and show various ways to control the conversion process.

9.4.5.1 Settling Time Using Synchronization

The SYNC/PWDN pin and SYNC command allow direct control of conversion timing. Issue a SYNC command or toggle the SYNC/PWDN pin after changing the analog inputs to restart conversions (see the Conversion Control and Synchronization section for more information). The conversion begins when SYNC/PWDN is taken high, thus stopping the current conversion, and restarting the digital filter. As soon as SYNC/PWDN goes low, the DRDY output goes high and remains high during the conversion. DRDY goes low after the settling time (t₁₈, listed for each data rate in Table 12), indicating that data are available. There is no need to ignore or discard data after synchronization. Figure 35 shows the data retrieval sequence following synchronization.

Figure 35. Data Retrieval After Synchronization

9.4.5.2 Settling Time Using Single-Shot Mode

To reduce power consumption in the ADS1257, perform single-shot conversions using the STANDBY command. The sequence for the STANDBY command is shown in Figure 36. Issue the WAKEUP command from standby mode to begin a single-shot conversion. When using single-shot mode, an additional delay is required for the modulator to power up and settle. This delay may require up to 64 modulator clocks (64 · 4 · t_(CKLIN)), or 33.3 μs for a 7.68-MHz master clock. Following the settling time (t₁₈ + 256 · t_(CLKIN)), DRDY goes low, indicating that the conversion is complete and data can be read using the RDATA command. The ADS1257 settles in a single cycle; there is no need to ignore or discard data. Following the data read cycle, issue another STANDBY command to reduce power consumption. When ready for the next measurement, repeat the cycle starting with another WAKEUP command.

Figure 36. Single-shot Conversions Using the STANDBY Command

9.4.5.3 Settling Time Using the Input Multiplexer

The most efficient way to cycle through the inputs is to change the multiplexer setting immediately after DRDY goes low. Changing the multiplexer before reading the data allows the ADS1257 to start sampling the new input channel sooner. Figure 37 demonstrates efficient input cycling. There is no need to ignore or discard data while cycling through the channels of the input multiplexer because the ADS1257 data are fully settled when DRDY goes low.

Figure 37. Cycling the ADS1257 Input Multiplexer

Step 1: When DRDY goes low (indicating that data are ready for retrieval), update the MUX register using the WREG command. For example, setting MUX to 23h selects AIN_P = AIN2, AIN_N = AIN3.

Step 2: Restart the conversion process by issuing a SYNC command followed by a WAKEUP command. Follow timing specification t₁₁ between commands.

Step 3: Read the data from the previous conversion using the RDATA command. Repeat this process when DRDY goes low.

Table 13 gives the effective overall throughput (1 / t₁₉) when cycling the input multiplexer. The values for throughput (1 / t₁₉) assume the multiplexer is changed with a 3-byte WREG command and f_(SCLK) = f_(CLKIN) / 4.

Table 13. Multiplexer Cycling Throughput⁽¹⁾

DATA RATE (SPS)	CYCLING THROUGHPUT (1 / t19) (Hz)
2.5	2.5
5	5
10	10
15	15
25	25
30	30
50	50
60	59
100	98
500	456
1000	837
2000	1438
3750	2165
7500	3043
15,000	3817
30,000	4374

(1) f_(CLKIN) = 7.68 MHz.

9.4.5.4 Settling Time while Continuously Converting

After a synchronization, input multiplexer change, or wakeup from standby mode, the ADS1257 continuously converts the analog input. The conversions coincide with the falling edge of DRDY. While continuously converting, the settling time is given by a number of DRDY periods, as shown in Table 14. The DRDY period equals the inverse of the selected data rate.

Table 14. Data Settling Delay Versus Data Rate

DATA RATE (SPS)	SETTLING TIME (DRDY PERIODS)
2.5	1
5	1
10	1
15	1
25	1
30	1
50	1
60	1
100	1
500	1
1000	1
2000	1
3750	1
7500	2
15,000	3
30,000	5

If there is a step change on the input signal while continuously converting, perform a synchronization operation to start a new conversion. Otherwise, the next data represent a combination of the previous and current input signal. Figure 38 shows an example of readback in this situation.

Figure 38. Step Change on V_IN While Continuously Converting for Data Rates ≤ 3750 SPS

9.4.6 Calibration

Minimize offset and gain errors by using the ADS1257 internal calibration features. Figure 39 shows the calibration block diagram. Offset errors are corrected with the offset calibration registers (OFC2, OFC1, and OFC0). Full-scale errors are corrected with the full-scale calibration registers (FSC2, FSC1, and FSC2). Each of these registers are 8-bits with full read and write access. The OFC[2:0] registers and the FSC[2:0] registers both form 24-bit calibration words, referred to as OFC and FSC, respectively.

Figure 39. Calibration Block Diagram

The output of the ADS1257 after calibration is shown in Equation 4.

Equation 4.

where

• α and β vary with data rate settings shown in Table 15 along with the ideal values (assumes perfect analog performance) for OFC and FSC.
• OFC is a binary twos complement number that can range from −8,388,608 to +8,388,607.
• FSC is unipolar ranging from 0 to 16,777,215.

The ADS1257 supports both self-calibration and system calibration for any PGA gain setting using a set of five commands: SELFOCAL, SELFGCAL, SELFCAL, SYSOCAL, and SYSGCAL. Calibration can be performed at any time; however, in many applications, the ADS1257 drift performance is low enough that a single calibration is all that is needed. DRDY goes high when calibration begins and remains high until settled data are ready. There is no need to discard data after a calibration. For best performance, issue a self-calibration command after power-up when the reference voltage has stabilized. Additionally, performing a reset automatically performs self-calibration. Calibration must be performed whenever the data rate, buffer configuration, or PGA gain changes.

9.5.1 Serial Interface

The SPI-compatible serial interface consists of four signals (CS, SCLK, DIN, and DOUT), and is used to read conversion data, read and write register data, and send ADC control commands. The programmable functions are controlled using a set of configuration registers. Data are written to and read from these registers through the serial interface. See the Serial Interface Timing Requirements section and Figure 1 for additional details on interfacing with the ADS1257.

9.5.1.4 Data Ready (DRDY)

The DRDY output is a status signal that indicates when a conversion has completed and new data are available to read. DRDY goes low when new conversion data are available, and returns high after all 24 bits are read back using the read data (RDATA) or read data continuous (RDATAC) command. If data are not retrieved, DRDY returns high while new conversion data are updated, as shown in Figure 40 (see the DRDY Update Timing Characteristics section for more information). Do not retrieve data while data are updating; reading data during this period results in invalid data.

Figure 40. DRDY With No Data Retreival

After changing the PGA gain, data rate, buffer setting, sensor-detect current-source setting, or writing to the OFC or FSC registers, perform a synchronization operation to restart conversions and force DRDY high. DRDY stays high until valid data are ready. If auto-calibration is enabled (by setting the ACAL bit in the STATUS register), DRDY goes low after self-calibration is complete and new data are valid. Exiting standby or power-down mode, or performing a reset or SYNC command also forces DRDY high. DRDY goes low again when valid data are ready.

9.5.2 Data Format

The ADS1257 outputs 24 bits of data in binary twos complement format. The least significant bit (LSB) has a value of (4 · V_REF / gain) / 2²⁴ V. A positive full-scale input produces an output code of 7FFFFFh, and the negative full-scale input produces an output code of 800000h. The output clips at these codes for signals exceeding full-scale. Table 20 summarizes the ideal output codes for different input signals.

9.5.3 Command Definitions

The commands summarized in Table 21 control the operation of the ADS1257. All of the commands are stand-alone except for read data (RDATA) and the the register reads and writes (RREG, WREG) which require a second command byte plus data. Additional command and data bytes may be shifted in without delay after the first command byte. The ORDER bit in the STATUS register sets the order of the bits within the output data. CS must stay low during the entire command sequence.

9.5.3.2 RDATA: Read Data

Issue the RDATA command after DRDY goes low to read a single conversion result. After all 24 bits are shifted out on DOUT, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY does not return high until new data are updated. See the Serial Interface Timing Requirements for the required delay between the end of the RDATA command and the beginning of data shift on DOUT: t₆.

Figure 41. RDATA Command Sequence

9.5.3.3 RDATAC: Read Data Continuous

Issue the RDATAC command after DRDY goes low to enter the read-data-continuous mode. This mode enables the continuous output of new data on each DRDY without the need to issue subsequent read commands. After all 24 bits are read, DRDY goes high. It is not necessary to read back all 24 bits, but DRDY does not return high until new data are updated. This mode is terminated by the stop-read-data-continuous command (SDATAC). Terminate the read-data-continuous mode before reading and writing the device register settings. See the Serial Interface Timing Requirements section for the required t₆ delay between the end of the RDATAC command and the beginning of shifting data on DOUT.

Figure 42. RDATAC Command Sequence

In read-data-continuous mode, shift out data by sending NOP commands. Three NOP commands are required to retrieve all 24 bits of data. The read data continuous mode terminates if input_data equals the SDATAC or RESET command in any of the three bytes on DIN.

Figure 43. DIN and DOUT Command Sequence During Read Continuous Mode

NOTE

Do not use read-data-continuous mode if DIN and DOUT are connected together, if DRDY is not used, or if reading data cannot be completed before the next DRDY falling edge.

9.5.3.4 SDATAC: Stop Read Data Continuous

The SDATAC command ends read-data-continuous mode and allows the device registers to be read or modified. The SDATAC command must be issued after DRDY goes low and completed before DRDY goes high.

Figure 44. SDATAC Command Sequence

9.5.3.5 RREG: Read from Registers

Use the RREG command to output the data from up to 11 configuration registers starting at the register address specified as part of the command. The number of registers read is one plus the second byte of the command. If the count exceeds the remaining registers, the addresses wrap back to the beginning. Exit read-data-continuous mode (with the SDATAC command) before issuing a RREG command.

First command byte: 0001 rrrr, where rrrr is the address of the first register to read.

Second command byte: 0000 nnnn, where nnnn is the number of bytes to read – 1. See the Serial Interface Timing Requirements section for the required delay between the end of the RREG command and the beginning of shifting data on DOUT: t₆.

Figure 45. RREG Command Example: Read Two Registers Starting From Register 01h (MUX)

9.5.3.6 WREG: Write to Register

Use the WREG command to write to the configuration registers starting at the register address specified as part of the command. The number of registers that are written is one plus the value of the second byte in the command. If auto-calibration is enabled, writing to the PGA[2:0], DR [7:0] or BUFEN fields starts a self-calibration. Exit read-data-continuous mode (with the SDATAC command) before issuing a WREG command.

First command byte: 0101 rrrr, where rrrr is the address of the first register to be written.

Second command byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.

Data bytes: one or more data bytes to be written to the device registers.

Figure 46. WREG Command Example: Write Two Registers Starting From 03h (DRATE)

9.5.3.12 STANDBY: Standby Mode / Single-shot Mode

The STANDBY command puts the ADS1257 into a low-power standby mode. After issuing the STANDBY command, no more activity on SCLK may occur while CS is low, because SCLK activity interrupts standby mode. SCLK activity does not interrupt standby mode while CS is high. To exit standby mode, issue the WAKEUP command. This command can also be used to perform single conversions (see the Settling Time Using Single-Shot Mode section for more details). The STANDBY command must be issued after DRDY goes low.

Figure 47. STANDBY Command Sequence

9.5.3.14 SYNC: Synchronize the Analog-to-Digital Conversion

The SYNC command synchronizes the analog-to-digital conversion. To use the SYNC command, shift in the SYNC command followed by the WAKEUP command. Synchronization occurs on the first CLKIN rising edge after the first SCLK rising edge used to shift in the WAKEUP command. See the Serial Interface Timing Requirements section for the required delay between the end of the SYNC command and the beginning of the WAKEUP command: t₁₁.

Figure 48. SYNC Command Sequence

Table 22. Register Map

9.6.1 STATUS: Status Register (address = 00h) [reset = x1h]

9.6.2 MUX : Input Multiplexer Control Register (address = 01h) [reset = 01h]

9.6.3 ADCON: ADC Control Register (address = 02h) [reset = 20h]

9.6.4 DRATE: ADC Data Rate Register (address = 03h) [reset = F0h]

9.6.5 IO: GPIO Control Register (address = 04h) [reset = E0h]

The states of these bits control the operation of the general-purpose digital I/O pins. The ADS1257 has two digital I/O pins: D0/CLKOUT and D1.

9.6.6 OFC0: Offset Calibration Register 0 (address = 05h) [reset = depends on calibration results]

9.6.7 OFC1: Offset Calibration Register 1 (address = 06h) [reset = depends on calibration results]

9.6.8 OFC2: Offset Calibration Register 2 (address = 07h) [reset = depends on calibration results]

9.6.9 FSC0: Full-Scale Calibration Register 0 (address = 08h) [reset = depends on calibration results]

9.6.10 FSC1: Full-Scale Calibration Register 1 (address = 09h) [reset = depends on calibration results]

9.6.11 FSC2: Full-Scale Calibration Register 2 (address = 0Ah) [reset = depends on calibration results]