ZHCSEA6B September   2015  – April 2016 ADS1257

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Serial Interface Timing Requirements
    7. 7.7  Serial Interface Switching Characteristics
    8. 7.8  RESET and SYNC/PWDN Timing Requirements
    9. 7.9  SCLK Reset Timing Requirements
    10. 7.10 DRDY Update Timing Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Multiplexer
      2. 9.3.2  Analog Input Buffer
      3. 9.3.3  Programmable Gain Amplifier (PGA)
      4. 9.3.4  Modulator Input Circuitry
      5. 9.3.5  Voltage Reference Inputs (REFP, REFN)
      6. 9.3.6  Clock Input (CLKIN)
      7. 9.3.7  Clock Output (D0/CLKOUT)
      8. 9.3.8  General-Purpose Digital I/O (D0, D1)
      9. 9.3.9  Open- and Short-Circuit Sensor Detection
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Frequency Response
        2. 9.3.10.2 50-Hz and 60-Hz, Line Cycle Rejection
        3. 9.3.10.3 Settling Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up
      2. 9.4.2 Reset
      3. 9.4.3 Standby Mode
      4. 9.4.4 Power-Down Mode
      5. 9.4.5 Conversion Control and Synchronization
        1. 9.4.5.1 Settling Time Using Synchronization
        2. 9.4.5.2 Settling Time Using Single-Shot Mode
        3. 9.4.5.3 Settling Time Using the Input Multiplexer
        4. 9.4.5.4 Settling Time while Continuously Converting
      6. 9.4.6 Calibration
        1. 9.4.6.1 Self-Calibration
          1. 9.4.6.1.1 SELFOCAL Command: Self-Offset Calibration
          2. 9.4.6.1.2 SELFGCAL Command: Self-Gain Calibration
          3. 9.4.6.1.3 SELFCAL Command: Self-Offset and Self-Gain Calibration
        2. 9.4.6.2 System Calibration
          1. 9.4.6.2.1 SYSOCAL Command: System-Offset Calibration
          2. 9.4.6.2.2 SYSGCAL Command: System-Gain Calibration
        3. 9.4.6.3 Auto-Calibration
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN) and Data Output (DOUT)
        4. 9.5.1.4 Data Ready (DRDY)
      2. 9.5.2 Data Format
      3. 9.5.3 Command Definitions
        1. 9.5.3.1  WAKEUP/NOP: Complete Synchronization or Exit Standby Mode
        2. 9.5.3.2  RDATA: Read Data
        3. 9.5.3.3  RDATAC: Read Data Continuous
        4. 9.5.3.4  SDATAC: Stop Read Data Continuous
        5. 9.5.3.5  RREG: Read from Registers
        6. 9.5.3.6  WREG: Write to Register
        7. 9.5.3.7  SELFCAL: Self-Offset and Self-Gain Calibration
        8. 9.5.3.8  SELFOCAL: Self Offset Calibration
        9. 9.5.3.9  SELFGCAL: Self Gain Calibration
        10. 9.5.3.10 SYSOCAL: System Offset Calibration
        11. 9.5.3.11 SYSGCAL: System Gain Calibration
        12. 9.5.3.12 STANDBY: Standby Mode / Single-shot Mode
        13. 9.5.3.13 RESET: Reset Registers to Default Values
        14. 9.5.3.14 SYNC: Synchronize the Analog-to-Digital Conversion
    6. 9.6 Register Map
      1. 9.6.1  STATUS: Status Register (address = 00h) [reset = x1h]
      2. 9.6.2  MUX : Input Multiplexer Control Register (address = 01h) [reset = 01h]
      3. 9.6.3  ADCON: ADC Control Register (address = 02h) [reset = 20h]
      4. 9.6.4  DRATE: ADC Data Rate Register (address = 03h) [reset = F0h]
      5. 9.6.5  IO: GPIO Control Register (address = 04h) [reset = E0h]
      6. 9.6.6  OFC0: Offset Calibration Register 0 (address = 05h) [reset = depends on calibration results]
      7. 9.6.7  OFC1: Offset Calibration Register 1 (address = 06h) [reset = depends on calibration results]
      8. 9.6.8  OFC2: Offset Calibration Register 2 (address = 07h) [reset = depends on calibration results]
      9. 9.6.9  FSC0: Full-Scale Calibration Register 0 (address = 08h) [reset = depends on calibration results]
      10. 9.6.10 FSC1: Full-Scale Calibration Register 1 (address = 09h) [reset = depends on calibration results]
      11. 9.6.11 FSC2: Full-Scale Calibration Register 2 (address = 0Ah) [reset = depends on calibration results]
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Digital Interface Connections
      3. 10.1.3 Analog Input Filtering
      4. 10.1.4 External Reference
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Detailed Design Procedure for ±10-V Input
          1. 10.2.2.1.1 Absolute Input Voltage Range
          2. 10.2.2.1.2 Differential Input Voltage Range
          3. 10.2.2.1.3 Level-Shifted Resistor Divider Sizing
          4. 10.2.2.1.4 Input Filtering
          5. 10.2.2.1.5 Register Settings for ±10-V Input
          6. 10.2.2.1.6 Voltage Input Design Variations
        2. 10.2.2.2 Detailed Design Procedure for 4-mA to 20-mA Input
          1. 10.2.2.2.1 PGA Gain Selection
          2. 10.2.2.2.2 Current-Sense Resistor Sizing
          3. 10.2.2.2.3 Register Settings for 4-mA to 20-mA Input
          4. 10.2.2.2.4 Current Input Design Variations
      3. 10.2.3 Application Curves
    3. 10.3 Dos and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

11 Power Supply Recommendations

The ADS1257 requires an analog (AVDD) and digital (DVDD) power supply. The analog power supply is independent of the digital power supply. The digital supply sets the general-purpose digital I/O logic levels for D0 and D1. The analog and digital sections of the ADC are not internally isolated, and the analog and digital grounds (AGND, DGND) must be connected together. Output voltage ripple produced by switch-mode power supplies can interfere with the ADC, and result in reduced performance. Use low-dropout regulators (LDOs) to reduce the power-supply ripple voltage produced by switch-mode power supplies.

11.1 Power-Supply Sequencing

The analog and digital power supplies can be sequenced in any order during power up. Apply the external reference voltage and external clock source after the analog and digital power supplies have settled. Wait at least 8192 clock cycles (nominally 1.1 ms) before communicating with the device, and reset the device to help avoid improper operation.

NOTE

Do not apply any signal to the ADS1257 prior to power-up. In cases where applying a signal is unavoidable, limit the current in order to keep input signals within the Absolute Maximum Ratings.

11.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. AVDD and DVDD must be decoupled with at least a 0.1-μF capacitor, as shown in Figure 60. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance connections. Use multilayer ceramic chip capacitors (MLCCs) with low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling. Avoid the use of vias for connecting decoupling capacitors whenever possible. If a via is required, the use of multiple vias in parallel lower the inductance of the connection; for example, when connecting to an internal ground plane layer. Connect the analog and digital ground pins together as close to the device as possible.
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