The digital filter decimates and filters the modulator data to provide high-resolution output data. By adjusting the amount of filtering though the OSR, trade-offs can be made between output data noise and bandwidth. Increasing the OSR reduces output data noise while decreasing the signal bandwidth.

As shown in Figure 7-10, the sample rate converter (SRC) receives data from the modulator prior to the digital filter block. See the Voltage Reference InputTiming DiagramsVoltage Reference InputSample Rate ConverterSample Rate Converter section for details.

Figure 7-10 Digital Filter Block Diagram

The digital filter consists of three sections: a variable-decimation sinc filter; a variable-coefficient, fixed-decimation FIR filter; and a programmable high-pass filter (IIR). The desired filter sections are selected by the FILTER[1:0] bits of the CONFIG0 register. The sinc filter provides partially filtered data, bypassing the FIR and HPF filters and the user calibration stage. For fully filtered data, select the FIR filter option. The IIR filter stage removes dc and low-frequency data. The FIR and the combined FIR + IIR filter are routed to the user calibration block and output code clipping block. See the Offset and Gain CalibrationOffset and Gain CalibrationOffset and Gain Calibration section for details of user calibration.