8.3.1 Flexible Routing Switch

The flexible routing switch can connect the inputs of the three analog front-end channels as well as the inputs of the analog pace channel to any of the 6 input pins. This allows system flexibility and even on-the-fly reconfiguration of the ECG monitoring system. For test purposes, the flexible routing switch can short the differential input pins of a channel or connect a differential reference signal to the input of a channel. This reference voltage can be applied with both positive and negative polarity. This feature allows to measure relative mismatches between channels, such as offset and gain mismatches. Additionally, there is an option to route a fraction of the battery voltage (the voltage source connected to the VDD pin) to an input channel. This allows the ADS1293 to monitor the state of charge of the battery.

The switch path inside the flexible routing switch is illustrated in Figure 17. The figure shows the switch path for a single channel. All channels are completely identical. The switches are controlled by the registers FLEX_CH1_CN, FLEX_CH2_CN, FLEX_CH3_CN, and FLEX_VBAT_CN, which are described in the Input Channel Selection Registers.

Figure 17. Flexible Routing Switch for Channel 1

It should be noted that the switches that control the input selection for the analog front-end channels have a certain priority. If the battery voltage monitoring mode is enabled by programming the VBAT_MONI_CHx bit in the FLEX_VBAT_CN register, then the POSx and NEGx bits programmed in the FLEX_CHx_CN register no longer have any effect. The battery voltage monitoring mode thus takes priority; this is shown in the first row of Table 1. Furthermore, the test features take second priority over the input pin selection. If the TSTx bit of the FLEX_CHx_CN register are not zero, then the POSx and NEGx bits are essentially ignored, and the test features will take priority as seen in Table 1. The TSTx, POSx, and NEGx bits are described in the Input Channel Selection Registers.

8.3.2 Battery Monitoring

The battery voltage monitoring mode is enabled by setting bit VBAT_MONI_CHx = 1 in the FLEX_VBAT_CN register. Also, the instrumentation amplifier of the selected channel must be shut down by setting SHDN_INA_CHx = 1 in the AFE_SHDN_CN register. In this mode, the positive input, POSx, of the sigma-delta modulator will sample the voltage supplied on the VDD pin. At the same time, the negative input, NEGx, of the sigma-delta modulator will sample the reference voltage, V_REF, generated on or provided to the CVREF pin. As a result, the output signal of the sigma-delta modulator is a measure for (V_BAT-V_REF). In this operation, the sigma-delta modulator works with a modified gain factor, and the battery voltage, V_BAT, can be calculated as follows:

Equation 1.

In this equation, V_REF equals 2.4 V if the internal reference voltage generator is used, and ADC_MAX represents the maximum output code of the ADC, which would correspond to a theoretical 2.4-V signal at the input of the sigma-delta modulator. The value of ADC_MAX is dependent on the configuration of the digital filters, and the corresponding ADC_MAX values are listed in Table 8 through Table 11.

The battery monitoring mode is targeted for battery operated systems within a voltage range of 2.4 V to 4.8 V. The battery monitoring mode cannot be used when the ADS1293 is powered from a regulated 5-V supply because it risks saturating the sigma-delta modulator. There is a also a low battery alarm that is implemented independently from the battery monitoring mode, which will trigger a battery alarm when the supply voltage is below 2.7 V (see the BATLOW description in Alarm Functions).

8.3.3 Test Mode

If the battery voltage monitoring function is not enabled, and if bit TSTx = 01 (see the Input Channel Selection Registers section), then a positive DC test signal is provided to the input of the instrumentation amplifier. If TSTx = 10, then that same test signal is provided but with negative polarity. The expected ADC output code can be calculated as follows:

Equation 2.

In Equation 2, the positive or negative DC test signal V_TEST = V_REF/12. Note that this test mode is not a gain calibration since V_TEST and V_REF are generated by the same reference; however, it can be used as a self-test or to measure gain mismatches between channels.

When TSTx = 11, the inputs of the instrumentation amplifier in the channel can be shorted to provide a zero test signal. The expected ADC output code equation can be simplified to:

Equation 3.

For both equations, the value of ADC_MAX corresponding to a given decimation configuration can be obtained from Table 8 through Table 11.

8.3.4 Analog Front-End

The ADS1293 contains three analog front ends that convert a differential analog voltage into a digital signal. Each analog front end consists of an instrumentation amplifier (INA), a sigma-delta modulator (SDM), and a digital filter.

8.3.5 Instrumentation Amplifier (INA)

The instrumentation amplifier provides a high input impedance to interface with signal sources that may have relatively high output impedance, such as ECG electrodes. The maximum differential input voltage range of the Sigma-Delta Modulator (SDM) behind the INA is ±1.4 V, and the gain of the INA is 3.5x. Therefore, the maximum differential input voltage of the INA is ±400 mV.

The input common-mode voltage range (CMVR) of the INA is 0.95 V to VDD-0.95 V. If the input differential voltage range is limited to smaller values, then the CMVR can be somewhat extended. If the differential input signal is limited to VIN_MAX, the CMVR range can be defined as:

Equation 4.

The INA can be configured to operate in a low-power mode or in a high-resolution mode. The low-power mode consumes about 3 times less power than the high-resolution mode. However, the high-resolution mode has less noise than the low-power mode. Switching between these two modes is controlled by the EN_HIRES_CHx bits in the AFE_RES register.

When a channel is not in use, its INA can be shut down by programming the SHDN_INA_CHx bit in the AFE_SHDN_CN register, and its SDM can also be shut down by programming the SHDN_SDM_CHx bit in the AFE_SHDN_CN register.

8.3.6 Sigma-Delta Modulator (SDM)

The Sigma-Delta Modulator (SDM) takes the output signal of the INA and converts this signal into a high resolution bit stream that is further processed by the digital filters.

The SDM can operate at clock frequencies of 102.4 kHz or 204.8 kHz; these frequencies are generated internally. Running the SDM at 204.8 kHz results in a larger oversampling ratio, which improves the resolution of the signal recovered by the digital filters behind the SDM. However, running the SDM at a higher clock frequency will increase its power consumption, resulting in a tradeoff between resolution and power consumption.

The 102.4-kHz or 204.8-kHz clock frequency can be selected for each channel individually by programming the FS_HIGH_CHx bits in the AFE_RES register.

The SDM also features dithering to reduce tones in the system, a known by-product of Sigma-Delta converters. The dithering circuit is active by default and is automatically turned OFF when the input signal is larger than 40 mV.

8.3.7 Programmable Digital Filters

A programmable digital filter behind the Sigma-Delta Modulator (SDM) reconstructs the signal from the SDM output bit stream. The filter consist of three programmable SINC filters as shown in Figure 18. Each stage is a fifth order SINC filter.

Figure 18. Sinc Filters

The decimation rates (R1, R2, and R3) of the SINC filters are programmable as described in Table 2. Each of the three stages further filters and decimates the bit stream so that the output data rate (ODR) and bandwidth (BW) of the signal is reduced, and at the same time, the resolution is enhanced. A 16-bit digital signal with relatively high ODR and BW, but with somewhat limited resolution, is available after the second stage; this signal can be used for PACE pulse detection. That signal is further decimated by the third stage and results in a very high-resolution filtered 24-bit digital signal that is an accurate representation of the ECG signal.

The first stage sets the Standard PACE Data Rate (where the decimation rate R1 = 4) or the Double PACE Data Rate (where R1 = 2). Operating the device in the Double PACE Data Rate will double the ODR for the first stage (and therefore also for the subsequent stages). However, the BW of the first stage does not change in this mode; only the ODR is affected. By operating the device in the Double PACE Data Rate, the ODR of the PACE data is doubled, and thus, more accurate PACE pulse detection is possible. However, operating the device in the Double PACE Data Rate will increase its power consumption. The R1 decimation rate can be programmed for each of the three channels separately by using the R1_RATE register.

Programming the second stage (R2) to a low decimation rate sets a relatively high ODR and BW, but doing so will also increase the noise level. For digital PACE pulse detection, smaller values for R2 are recommended. The R2 decimation rate can be programmed using the R2_RATE register.

As the third stage decimation (R3) increases, the ODR and BW of the ECG decreases. When detecting an ECG signal, higher values of R3 are recommended. The R3 decimation rate for each channel can be individually programmed using the R3_RATE_CH1, R3_RATE_CH2, and R3_RATE_CH3 registers.

Table 8, Table 9, Table 10, and Table 11 illustrate how these decimation rates R1, R2, and R3 affect the ODR, BW, and RMS Noise of the PACE and ECG signals. In addition, the ODR and BW also depend on whether the SDM is running at a low (102.4kHz) or high (204.8 kHz) clock frequency (set by the FS_HIGH_CHx bits in the AFE_RES register). The RMS Noise of the PACE and ECG channels also depend on whether the instrumentation amplifier is running in low-power or high-resolution mode (set by the EN_HIRES bits in the AFE_RES register).

In summary, the output data rate of an ECG channel can be calculated as follows:

Equation 5.

And the output data rate of a PACE channel can be calculated as follows:

Equation 6.

Where f_S is the clock frequency of the modulator: 102.4 kHz, or 204.8 kHz.

8.3.8 Filter Settling Time

The low-pass filter frequency responses of the ECG and PACE SINC filters result in a settling time associated with their outputs as a response to a step input signal. This settling time is determined by the order of the filter, N, its differential delay, M, and the channel output data rate, ODR:

The ODR of the filter is a function of the sigma-delta's sampling frequency, f_S, and the filter decimation rates. The value of the ODR can be calculated using Equation 5 and Equation 6. For an ECG channel, the value of NxM = 5. For a pace channel NxM = 5 when operated in the Standard Pace Data Rate (R1 = 4), and NxM = 10 when operated in the Double Pace Data Rate (R1 = 2).

As a result, an unclamped pace signal applied to the filter input results in an ECG channel minimum settling time of:

A Standard Pace Data Rate operated pace channel will go through a minimum settling time of:

And a Double Pace Data Rate operated pace channel will go through a minimum settling time of:

8.3.9 Analog Pace Channel

The ADS1293 features an additional analog pace channel to process pulses from a pacemaker. The analog pace channel is suitable for low-power applications where the device can be configured for low data rates in ECG mode only, while an analog channel detects PACE pulses. This channel consists of a traditional three opamp instrumentation amplifier and is designed to amplify an ECG signal in a typical bandwidth, as specified in the Electrical Characteristics table, allowing for external circuitry to detect the PACE pulses. The analog pace implementation inside the ADS1293 is depicted in Figure 19. The analog pace channel is not limited to PACE detection; it is a full-analog channel that could be used to pre-amplify signals, for instance, from a respiration sensor.

The output voltage of the analog pace channel is:

Where Vinp and Vinm are the positive and negative inputs of the analog pace channel. The input pins of this channel can be selected in the FLEX_PACE_CN register and can connect to any of the IN1 through IN6 pins. Note there is no battery monitoring option available through this channel. There is, however, the reference voltage test mode available as described in Test Mode.

Figure 19. Analog Pace Channel Instrumentation Amplifier

The output of the analog pace channel can be multiplexed to the WCT or RLDIN pin using the AFE_PACE_CN register. When PACE2RLDIN = 1, the output is routed to the RLDIN terminal, while internally the positive input of the Right-Leg Drive amplifier is connected to the RLDREF pin. When PACE2WCT = 1, the output is routed to the WCT terminal, and the WCT terminal is disconnected from the Wilson output. In this case, the Wilson output can still be connected internally to the IN6 pin using the WILSON_CN register. The analog pace channel is disabled when SHDN_PACE = 1 to save power when it is not used.

The analog pace channel is designed to drive a high pass filter and can directly drive a capacitive load of 100 pF.

For analog pace detection, TI recommends having a band pass filter at the output of the analog pace channel, amplify the resulting signal with a relatively high bandwidth amplifier, and compare the amplified pulses with a relatively high speed window comparator. The bandwidth of the band pass filter, gain of the amplification, and the thresholds of the window comparator should be tuned so the comparators trigger on pacemaker pulses, but not to other signals present in the ECG environment.

8.3.10 Wilson Reference

The ADS1293 features a Wilson reference block consisting of three buffer amplifiers and resistors that can generate the voltages for the Wilson Central Terminal or Goldberger terminals. Each of the three buffer amplifiers can be connected to any input pin, IN1 through IN6, by programming the WILSON_EN1, WILSON_EN2, and WILSON_EN3 registers. A buffer that is not connected to an input pin is automatically disabled. When disabled, the buffers have a high-output impedance.

Figure 20. Wilson Reference Generator Circuit

The output of the Wilson Reference can be routed internally to IN6, and the outputs of the Goldberger reference can be routed internally to IN4, IN5 and IN6. This is configured in the WILSON_CN register. If routed externally, TI strongly recommends shielding these connections, which due to their high-output impedance, are prone to pick up external interference.

8.3.11 Common-Mode (CM) Detector

The Common-Mode Detector averages the voltage of up to six input pins. Its output can be used in a right-leg drive feedback circuit. The selection of the input pins that contribute to the average is configured in the CMDET_EN register. The Common-Mode Detector is automatically disabled when no input pin is selected.

Figure 21. Common-Mode Detector Circuit

8.3.12 Right-Leg Drive (RLD)

The RLD is a programmable operational amplifier that is intended to control the common-mode level of the patient connected through electrodes to the ADS1293 and thereby improving the AC CMRR of the overall ECG system. In a typical ADS1293 application, the common-mode level of the patient's body is measured by the Common-Mode Detector described in the previous section. The CMOUT is compared by the RLD to the reference voltage present on the RLDREF pin. When used in an inverting amplifier topology, the right-leg electrode is driven by the RLD to counter any differences between the reference voltage and the detected common-mode level. This reduces the amount of power-line common-mode interference.

The negative input terminal of the RLD op-amp is always connected to the RLDINV pin. By default, the positive input terminal of the RLD op-amp is routed to the RLDIN pin. However, when bit PACE2RLDIN = 1 in the AFE_PACE_CN register, the positive input terminal is routed to the internally to the RLD reference. This will allow connecting the output of the analog pace instrumentation amplifier to the RLDIN pin. The output of the RLD operational amplifier is always connected to the RLDOUT pin, and in addition, can be connected to one of the IN1-IN6 terminals by programming the SELRLD bit in the RLD_CN register. The RLD circuit can be shut down in the same register by setting bit SHDN_RLD = 1.

Figure 22. Right-Leg Drive Circuit

8.3.13 Capacitive Load Driving

The bandwidth and capacitive load driving capability of the RLD can be configured in the RLD_CN register to achieve an optimal tradeoff of power consumption. Table 5 lists the power consumption corresponding to different configuration scenarios.

8.3.14 Error Status: RLD Rail

The RLD amplifier incorporates a near to rail alarm function that is triggered when the output of the op-amp is below 0.2 V or above VDD-0.2 V. The alarm is reported to the RLDRAIL bit in the ERROR_STATUS register and indicates that the RLD's feedback loop has difficulty maintaining a constant voltage on the patient’s body. In this case, the common-mode on the patient’s body may drift away from its target value, but it may still be within the proper input common-mode voltage range of the ADS1293, and the ECG signal data acquisition can continue. When the common-mode on the patient’s body is outside the operation range of the ADS1293, the CMOR error will be raised, as described in the previous section. System alarms are filtered by the digital circuitry (see Error Filtering), and for this reason, the master clock must be active in order to capture an alarm.

8.3.15 Lead-Off Detection (LOD)

The lead-off detect (LOD) block of the ADS1293 can be used to monitor the connectivity of the 6 input pins to electrodes. The LOD block injects a programmable DC or AC excitation current into selected input pins and detects the voltages that appear on the input pins in response to that current. If a lead is not making a proper contact, then the electrode impedance will be high, and as a result, the voltage in response to a small test current will be relatively large, while the voltage for a well-connected lead will be small.

The LOD block can work in one of the three following modes: 1) DC lead-off detect, 2) analog AC lead-off detect or 3) digital AC lead-off detect. All three LOD modes use a common DAC that provides a programmable reference current. This reference current is used to set the magnitude of the test current for lead-off detection. The amplitude of the excitation current used for lead-off detection can be programmed in the LOD_CURRENT register, where codes 0 to 255 result in currents ranging from 0 to 2.040 µA in steps of 8 nA.

The complete LOD block can be shut down by programming the SHDN_LOD bit to 1 in the LOD_CN register.

8.3.16 DC Lead-Off Detect

The LOD block can be configured for DC LOD mode by programming a 0 in the SELAC_LOD bit of the LOD_CN register. In the DC LOD mode, a DC test current can be injected into any of the six input pins by setting the corresponding bit EN_LOD[x] of the LOD_EN register. Programming a bit to 1 in this register enables a switch that allows a copy of the current programmed into the DAC to be injected into the desired input pins, as shown in the simplified block diagram of Figure 23.

Figure 23. Simplified DC Lead-Off Detect Block Diagram

For the selected input pins, a Schmitt-trigger comparator then compares the voltage that appears on the pin to (VDD-0.5 V). The result of this comparison can be accessed through the corresponding OUT_LOD[x] bit of the ERROR_LOD register. If a lead is off, then the injected current has no return path-to-ground, and as a result, the voltage on the associated input pin will rise towards VDD. This is detected by the comparator and is used as a signal to indicates the lead is not properly connected.

It is important to note that the lead-off detection circuit requires a low impedance return path from the right-leg electrode-to-ground, such as a voltage reference or the RLD amplifier output. Without a proper low impedance return path for the LOD currents, all enabled LOD pins will report a lead disconnected.

8.3.17 Analog AC Lead-Off Detect

DC lead-off detection cannot be used when using capacitively coupled electrodes, such as dry electrodes, because they have a high-DC impedance that will block DC test currents. In this case, the analog AC LOD block can be used. Contrary to the DC LOD, the AC LOD injects AC excitation currents with programmable amplitudes and frequencies into the desired lead.

To operate the LOD in analog AC LOD mode, the SELAC_LOD and the ACAD_LOD bits of the LOD_CN register must be set to 1.

A simplified block diagram of the analog AC LOD block is shown in Figure 25. The AC excitation frequency can be programmed by a 7-bit number, ACDIV_LOD, and a division factor, ACDIV_FACTOR, in the LOD_AC_CN register. The register sets the output frequency of the divider to a rate of:

Where K is 1 if the ACDIV_FACTOR bit equals 0, and K is 16 if the ACDIV_FACTOR bit equals 1. For instance, ACDIV_LOD = 0 and ACDIV_FACTOR = 0 result in an excitation frequency of 12.5 kHz, which is the maximum excitation frequency.

Complimentary driven switches, enabled by the EN_LOD[x] bits of the LOD_EN register, sink and source the AC excitation currents into the desired input pins. The resulting AC current has a frequency Φ and a peak-to-peak amplitude equal to the current programmed into the DAC. An AC coupled synchronous detector detects the amplitude of the AC voltage appearing on the lead. The detected amplitude is compared to a reference voltage by means of a Schmitt-trigger comparator. The comparator’s reference voltage level, as shown in Figure 24, is determined by a 2-bit reference DAC configured in the ACLVL_LOD bits of the LOD_CN register.

Figure 24. Analog AC Lead-Off Reference Levels

The comparator outputs can be accessed at the OUT_LOD[x] bit of the ERROR_LOD register. A high comparator output signal indicates that the AC voltage at the excitation frequency is larger than the programmed threshold, which indicates that the lead is not well connected.

The lead-off detection circuit requires a low-impedance return path from the right-leg electrode-to-ground, such as a voltage reference or the RLD amplifier output. Without a proper low-impedance return path for the LOD currents, all enabled LOD pins will report a lead disconnected.

Figure 25. Simplified Analog AC Lead-Off Detect Block Diagram

8.3.18 Digital AC Lead-Off Detect

The digital AC lead-off detect (LOD) allows for measurement of the impedance of the two electrodes connected to an AFE channel by measuring a signal through the AFE. In this mode, the lead-off detect current is injected in a balanced manner at the inputs of the AFE behind the flex routing switch. The AC test current is injected into the positive input of the AFE behind the flex routing switch; while at the same time, a similar test current with opposite sign is injected into the negative input of the AFE. Since the AFE has a very high input impedance, the current injected into the positive input pin cannot flow into the AFE. Instead, it will flow through the flex routing switch, via the positive input electrode into the patient, and then back through the negative input electrode and via another path in the flex routing switch towards the negative input of the AFE, where it is cancelled by the current injected at that point. As a result of this test current, an additional AC voltage input will occur at the input of the AFE with a frequency equal to the frequency of the AC LOD test signal frequency. The magnitude of this voltage equals the magnitude of the AC LOD test current (programmed into the CUR_LOD bit in the LOD_CURRENT register) multiplied by the impedances of the two electrodes routed to the AFE input in series. This AC voltage will be digitized by the AFE, and the result is available in the digital AFE output signals. The lead connectivity can be determined in the digital domain by applying an FFT to the digital data and by measuring the amplitude of the tone at the AC LOD excitation frequency. It should be noted that the digital AC LOD can only determine the series connectivity of the two leads attached to the inputs of a differential channel, and hence the connectivity of the individual input pins can only be determined by the DC or the analog AC LOD.

Figure 26. Simplified Digital Analog AC Lead-Off Detect Block Diagram

Figure 26 shows a simplified block diagram of the digital AC LOD. Follow the procedures below to activate the Digital AC LOD:

1. Select the Digital AC lead-off mode by setting bit SELAC_LOD = 1 and ACAD_LOD = 0 in the LOD_CN register.
2. Program the excitation frequency Φ by using the ACDIV_LOD and ACDIV_FACTOR bits in the LOD_AC_CN register. See the equation in Analog AC Lead-Off Detect.
3. Enable which channel the digital AC LOD will be applied to by selecting the EN_LOD[2:0] bits in the LOD_EN register. These bits correspond to the AFE channels CH3 to CH1 from MSB to LSB, respectively.
4. Determine the phase of the injected current to the AFE channels by programming the EN_LOD[5:3] bits in the LOD_EN register.

The EN_LOD[5:3] bits determine the phase of the injected current to the AFE channels CH3 to CH1 from MSB to LSB, respectively. A bit set to 1 means that the corresponding channel will receive an anti-phase excitation current in respect to the frequency divider's phase. In some applications, it may be necessary to invert the sign of the digital AC lead-off test current on a channel. Consider an example where the first AFE is configured through the flexible routing switch to measure the voltage between IN1 and IN2, and the second AFE is configured through the flexible routing switch to measure the voltage between IN2 and IN3.

In this configuration, if digital AC LOD test currents are applied to the inputs of both AFEs, the test current that is applied to the negative input of the first AFE and the test current that is applied to the positive input of the second AFE are both flowing through IN2. Depending on the sign of the test current in the second AFE, these currents can add up or cancel each other. If the currents add up, the system will correctly measure the differential input impedance on both AFE channels. If the currents on IN2 cancel, the test current will only flow through IN1 and IN3, and the impedance of the electrode connected to IN2 cannot be measured. To apply the digital AC LOD to CH3 and CH2, set EN_LOD[2] = 1 and EN_LOD[1] = 1. Then, by programming EN_LOD[5] = 0 and EN_LOD[4] = 1, CH3 and CH2 will receive excitation currents in-phase and anti-phase, respectively.

8.3.19 Clock Oscillator

The ADS1293 is designed to operate from a 409.6-kHz clock. This clock can be generated by an on-chip crystal oscillator or provided externally on the bi-directional CLK. The high-accuracy low-power on-chip crystal oscillator will work with an external 4.096 MHz crystal connected between the XTAL1 and XTAL2 pins, each of which must be loaded with a 20-pF capacitor to get an accurate oscillation frequency. The output frequency of the on-chip crystal oscillator is divided by 10 to generate the required 409.6-kHz clock frequency as shown in Figure 27.

Figure 27. Block Diagram of the Clock

Even though the required oscillation frequency of the external crystal is rated at 4.096 MHz, both the oscillator and the chip can tolerate a wider crystal oscillation frequency (3.7 MHz to 4.5 MHz). Note though that the output data rate and bandwidth of the SINC filters given in Table 8 through Table 11 will scale according to the crystal oscillation frequency.

When the internal clock is used, the generated clock can be brought off chip through the CLK pin. Its output driver is enabled by configuring bit EN_CLKOUT = 1 in the OSC_CN register, allowing a multichip system to operate synchronously from a single crystal oscillator. Setting bit STRTCLK = 1 allows the internal 409.6-kHz clock to propagate to the digital circuitry and to the output driver of the CLK pin.

The internal crystal oscillator can be shut down to save power or when the clock of the device is provided externally. Configuring bit SHDN_OSC = 1 powers down the internal crystal oscillator and enables the input driver of the CLK pin. The external clock should have a frequency of 409.6kHz with a duty cycle of 50% to get the SINC filter bandwidth given in Table 8 through Table 11. The chip can tolerate a wider frequency range and clock duty cycle on this pin (see the External Clock Frequency and the External Clock Duty Cycle parameters in the Clock section of the Electrical Characteristics table) in exchange of scaling up or down the bandwidth of the SINC filters. Setting bit STRTCLK = 1 allows the external 409.6 kHz clock to propagate to the digital circuitry.

The STRTCLK bit is designed to ensure all critical blocks of the chip get a clean clock start. The clock source should first be configured and allowed to start up using the SHDN_OSC and EN_CLKOUT bits, and subsequently, the STRTCLK bit can be set high.

The oscillator control register bits are summarized in Table 6. In a multichip system, the CLK pins of the master and slaves should be connected together. The master should be configured to generate a clock on the CLK pin while the slaves should use the CLK pin as a clock input source.

8.3.20 Synchronization

There are three filter timing generators implemented to support independent filter settings. Under normal conditions, the filters always start synchronized when the START_CON bit in the CONFIG register is set to 1, and will remain synchronized. Synchronization can also be continually enforced for the eventuality of a channel losing synchronization, and it can be used in single-chip and multiple-chip systems.

8.3.21 Single-Chip Multi-Channel Synchronization

The filter channels are synchronized when DRDYB assertion is at a fixed frequency and new data from each source is available at some integer multiple of DRDYB. This synchronization mode requires that the fastest output data source is selected to drive DRDYB in the DRDYB_SRC register.

The filter channels will start synchronized if the output data rates in all channels are the same or integer multiples of each other. Synchronization between channels will be continuously enforced as long as the slowest output source is selected as the synchronization source in the SYNCB_CN register. The SYNCB pin output driver can be disabled in a single-chip system, regardless of the synchronization source selected, and synchronization will continue to be enforced between channels. The SYNCB output driver is disabled programming bit DIS_SYNCBOUT=1 in the SYNCB_CN register.

8.3.22 Multichip Synchronization

Synchronization in a multiple ADS1293 system is achieved when all the devices share a common clock and synchronization source. The common clock source, f_OSC, can be driven from the CLK pin of an ADS1293 when its CLK pin output driver is enabled in the OSC_CN register. The common synchronization source can be driven from the SYNCB pin of the device with the slowest data rate in the system. An ADS1293 is configured as a synchronization source by enabling its SYNCB output driver and selecting the slowest data rate channel to drive the line in the SYNCB_CN register. The SYNCB_CN register of the other devices should be programmed to 0x40 to configure their SYNCB pins as inputs. When configured as an output, SYNCB is driven on the falling edge of f_OSC and when configured as an input, SYNCB is sampled on the rising edge of f_OSC.

8.3.23 Synchronization Errors

Detected synchronization events are reported to the ERROR_SYNC register. A phase error is generated when the phase of divided clocks of the timing generator has been adjusted to comply with the SYNCB input signal. A timing error is generated when the timing of the indicated channel has been updated to comply with the timing of the synchronization source, internal or external. By default, a synchronization error will propagate to the ALARMB output pin. Reporting of a synchronization error can be disabled in the MASK_ERR register.

8.3.24 Alarm Functions

The ADS1293 has multiple warning flags to diagnose possible fault conditions in the ECG-monitoring application. The warning flags can be read in the Error Status Registers. The system errors are filtered by the digital circuitry (see Error Filtering), and for this reason, the master clock must be active for the alarms to be reflected in the error registers.

1. ERROR_LOD: Indicates which input has a lead-off error. The lead-off detection was described in Lead-Off Detection (LOD) .
2. ERROR_STATUS: Contains the following error flags:
   • SYNCEDGEERR: This flag is raised when a synchronization error occurs, as described in Synchronization Errors.
   • CH3ERR: This flag is raised when one of the 5 LSBs or bit 6 of the ERROR_RANGE3 register is a logic 1. It indicates an out-of-range condition at the AFE in channel 3. These error conditions are described in Instrumental Amplifier Fault Detection and in Sigma-Delta Modulator Fault Detection.
   • CH2ERR: See above, but for channel 2.
   • CH1ERR: See above, but for channel 1.
   • LEADOFF: This error flag is raised when one of the OUT_LOD bits in the ERROR_LOD register is a logic 1.
   • BATLOW: This error flag is raised when the supply voltage of the ADS1293 drops below 2.7 V. This can be used as a warning sign to the microcontroller that the state of charge of a supply battery is almost below levels of operation. The ADS1293 is designed to function within specification for supplies larger than 2.7 V but communication the digital communication interface will work down to 2.4 V so that this alarm condition can still be communicated to the microcontroller. A low battery error propagates to the ALARMB pin unless the MASK_BATLOW bit in the MASK_ERR register is set to 1. System alarms are filtered by the digital circuitry (see Error Filtering), and for this reason, the master clock must be active in order to capture an alarm. There is also a battery voltage monitoring feature that can be used to monitor the state of charge of the battery during normal operation described in Battery Monitoring.
   • RLDRAIL: This error flag is raised when the output voltage of the right-leg drive amplifier is approaching the supply rails. The flag goes high when the output voltage of the common-mode detector is 200 mV away from either supply rail. This condition would occur if the common-mode on the patient’s body is far away from the target value and as a result the right-leg drive amplifier needs to deliver a lot of charge to the patient’s body to restore the common-mode voltage. In this scenario, the common-mode may still be inside the range of the instrumentation amplifier and the ECG signal may still be accurately acquired.
   • CMOR: The CMOR error flag is raised when the output voltage of the common-mode detector is 750 mV away from either supply rail. In this case, the common-mode voltage detected on the patient’s body is outside of the input CMVR where the instrumentation amplifier can process the full differential input signal (see Instrumentation Amplifier (INA)). When this flag is raised, the ECG signal accuracy may be lost.
3. ERROR_RANGE1, ERROR_RANGE2, ERROR_RANGE3: These registers contain the out-of-range error signals of the AFEs in the three channels. The flags in these registers are described in Instrumentation Amplifier Fault Detection and in Sigma-Delta Modulator Fault Detection.
4. ERROR_SYNC: This register contains flags that indicate certain synchronization errors have been detected. These errors have been described in Synchronization Errors.
5. ERROR_MISC: This register contains status flags for common-mode out-of-range, right-leg drive near rail and low battery errors.

8.3.25 Error Filtering

The alarms that are generated by the analog circuitry inside the ADS1293 are filtered by digital logic. Alarms will only be accepted if they are active for a number of consecutive digital clock cycles, which toggle on the falling edge of the 409.6-kHz oscillator clock. The number of digital clock cycles that an alarm will have to be active before it is accepted is programmable between 1 and 16 counts using the ALARM_FILTER register. This register contains two separate filter parameters. The 4 LSBs in this register program the filtering of the lead-off detect error bits. The 4 MSBs program the filtering of the instrumentation amplifier signal out-of-range errors, the sigma-delta input over range errors, and the CMOR, RLDRAIL and BATLOW errors.

8.3.26 ALARMB Pin and Error Masking

The ADS1293 has an ALARMB output pin. This open-drain output will go low when a new alarm condition occurs in the ERROR_STATUS register. The ALARMB pin can be used as an interrupt signal to a microcontroller to warn about error conditions that can potentially corrupt the data that is being collected so that the microcontroller can take appropriate preventive action. The functionality of the ALARMB pin is flexible and programmable using the MASK_ERR register. This register allows masking some of the errors in the ERROR_STATUS register so that certain alarm events will not trigger a high to low transition on the ALARMB pin.

8.3.27 Error Register Automatic Clearing Description

All error bits in the registers 0x18 through 0x1E are latched in a high state when an error occurs and will only return to zero after being read. The error bits will remember an error until the user reads the error. The sign bits in the CH1ERR, CH2ERR and CHR3ERR registers are latched on low to high transition of the DIF_HIGH transitions in the corresponding registers. In this way, when the differential signal goes out-of-range, the sign of the signal can also be detected when the alarm register is read. Upon read, the error bits will be cleared. If the error condition has disappeared before the error is read, the error bits will remain low after being read. For all error registers, except ERROR_STATUS, the error bits will return to their high state within a few internal clock cycles if the error condition is still present after a register read. The bits in the ERROR_STATUS register only respond to new errors. If an error persists after the ERROR_STATUS register is read, the error condition will not be reflected in the error status register and the ALARMB pin will not pulse low again.

8.3.28 Alarm Propagation

Figure 28 shows how the alarms propagate through the digital circuitry inside the ADS1293. The errors propagate from left to right. Synchronization errors are not filtered because they are generated synchronously inside the digital circuitry, and if they occur, they are latched in the ERROR_SYNC register. Lead-off detect errors are filtered by a counter programmed in the 4 LSBs of the ALARM_FILTER register and are latched in the ERROR_LOD register. The instrumentation amplifier out-of-range, sigma-delta over range, right-leg drive amplifier out-of-range, common-mode amplifier out-of-range and low battery signals are also filtered by a counter programmed in the MSBs of the ALARM_FILTER register. The out-of-range signals for the 3 channels are latched in the ERROR_RANGE1, ERROR_RANGE2 and ERROR_RANGE3 registers. The first 6 registers on the right-hand side of the circuit latch errors until the error is being read. After being read, the error bit will be reset, but it will return to a logic 1 if the internal alarm condition persists. After being filtered the alarms are all routed to a digital logic block that detects whether a new alarm has occurred. If this happens, the appropriate bit in the ERROR_STATUS register will be set and the ALARMB pin will be pulled down. The bits in the ERROR_STATUS register will be reset and the ALARMB pin will released when the ERROR_STATUS register is read.

Figure 28. Graphical Illustration of Alarm Propagation

8.3.29 Reference Voltage Generators

The common-mode and right-leg drive reference generates VDD/2.2 volts, which are present on the RLDREF pin. This reference is used as an internal common-mode reference, as the reference for the analog pace channel, and should be powered on at all times when a sigma-delta modulator is running. It can be powered down by programming bit SHDN_CMREF=1 in the REF_CN register. The RLDREF pin should have a 0.1-µF bypass capacitor-to-ground.

The internal reference, V_REF, generates 2.4 V, which are present on the CVREF pin. The CVREF pin must have a 1 µF bypass capacitor-to-ground with low ESR and is not designed to be loaded with other circuitry. This reference should also be powered on at all times when a sigma-delta modulator is running. It can be powered down programming bit SHDN_REF=1 in the REF_CN register. It is possible to provide the reference voltage externally on this pin when the internal reference generator is shut down.

All three voltage generators require a somewhat larger start up time compared to the other circuit blocks inside the ADS1293, which is why they are treated differently in the global power-down or standby states, as will be described in the next section.

8.3.30 Power Management

The ADS1293 has many features that allow the optimization of power consumption. The common-mode detector and right-leg drive amplifier can be configured to achieve the optimum AC performance to power consumption ratio in a given application environment. Almost all internal circuit blocks can be powered down to reduce power consumption. Table 7 lists the typical power consumption budget for all of the circuit blocks that can be individually powered down.

There are two master control bits, PWR_DOWN and STANDBY, in addition to the power-down control bits that are used to power-down an individual circuit block, and they are located in the CONFIG register. In the power-down mode, all circuits that can be powered down are powered down, irrespective of the state of their individual shutdown bits. With the PWR_DOWN bit, the entire ADS1293 can be quickly placed in its minimal current consumption state without needing to do many individual configuration register writes. The STANDBY bit operates in a similar manner, but it does not affect the state of the three voltage generators and the crystal oscillator inside the ADS1293, which require a somewhat longer time to start up. When placing the ADS1293 in standby mode, the power consumption is somewhat higher than in the power-down state but the ADS1293 can return to operation quicker. The difference between the current consumption in power-down and in standby depends on the logic state of the shutdown bits of the two reference voltage generators and the crystal oscillator, as described in Table 7.

Table 7 specifies the current consumption of the blocks that are always ON in the first row. The second group in the table specifies the current consumption of the two reference voltage generators and the crystal oscillator that are OFF in power-down mode but that remain active during standby mode. The last group of circuit blocks in the table specifies the current consumption of the other circuit blocks. The ADS1293 will need about 100 ms to return to operation after being powered down. The time to recover from standby is limited by the time latency of the programmable logic filters in the AFE channels, as described in the Filter Settling Time section.

8.4.1 Low Sampling Rate

The following tables summarize the output data rate, digital filter bandwidth and typical RMS noise of a channel for every decimation ratio combination possible when the sigma-delta modulator is configured for a sampling rate of 102.4 kHz. Table 8 shows the channel parameters when the standard pace data rate is selected, and Table 9 shows the channel parameters when the double pace data rate is selected. The sampling rate of the sigma-delta modulator is selected in the AFE_RES register and the pace data rate is selected in the R1_RATE register.

8.4.2 High Sampling Rate

The following tables summarize the output data rate, digital filter bandwidth and typical RMS noise of a channel for every decimation ratio combination possible when the sigma-delta modulator is configured for a sampling rate of 204.8 kHz. Table 10 shows the channel parameters when the standard pace data rate is selected, and Table 11 shows the channel parameters when the double pace data rate is selected. The sampling rate of the sigma-delta modulator is selected in the AFE_RES register and the pace data rate is selected in the R1_RATE register.

8.4.3 Ouput Code (ADC_OUT)

The ADC_OUT of the ADS1293 is due to a differential voltage applied between the positive and negative input terminals of the instrumentation amplifier and can be calculated with Equation 13:

Equation 13.

The reference voltage V_REF, equals to 2.4 V if the on-chip voltage reference is used. ADC_MAX represents the maximum output code of the ADC, which corresponds to a theoretical 2.4-V signal at the input of the SDM. The value of ADC_MAX changes with the configuration of the digital filters, and the corresponding value can be found in Table 8, Table 9, Table 10, and Table 11. Note that ADC_OUT equals ADC_MAX/2 for a 0V differential input.

8.5.1 Serial Digital Interface

A serial peripheral interface (SPI) allows access to the control registers of the ADS1293. The serial interface is a generic 4-wire synchronous interface compatible with SPI type interfaces used on many microcontrollers and DSP controllers.

8.5.2 Digital Output Drive Strength

The strength of the transistors driving the serial data out pin (SDO) can be programmed to four levels in the DIGO_STRENGTH register. The drive strength will affect the slope of the digital output signal edges, and the optimal drive strength will depend on the capacitive loading on the SDO pin, where larger capacitive loads require larger drive strength. The output drive strength configurability may help reduce interference from the SPI communication into the AFE signal path. In this sense, it is advised to use the lowest drive strength that works for a particular system.

8.5.3 SPI Protocol

A typical serial interface access cycle is exactly 16 bits long, which includes an 8-bit command field (R/WB + 7-bit address) to provide for a maximum of 128 direct access addresses, and an 8-bit data field. Figure 29 shows the access protocol used by this interface. Extended access cycles are possible and they are described in the Auto-Incrementing Address and Streaming sections.

Figure 29. Serial Interface Protocol

Each assertion of chip select bar (CSB) starts a new register access. The R/Wb bit in the command field configures the direction of the access operation; a value of 0 indicates a write operation and a value of 1 indicates a read operation. All output data is driven on the falling edge of the serial clock (SCLK), and for the 16-bit protocol, SDO read data is driven on the falling edge of clocks 8 through 15. All input data on the serial data in (SDI) pin is sampled on the rising edge of SCLK and is written into the register on the rising edge of the 16th clock. The user is required to deassert CSB after the 16th clock; if CSB is deasserted before the 16th clock, no data write will occur.

8.5.4 Random Register Access Protocol

The 16-bit protocol is useful for random address access. CSB must be asserted during 16 clock cycles of SCLK.

8.5.5 Auto-Incrementing Address

An access cycle may be extended to multiple registers by simply keeping the CSB asserted beyond the stated 16 clocks of the standard 16-bit protocol. In this mode, CSB must be asserted during 8*(1+N) clock cycles of SCLK, where N is the amount of bytes to write or read during the access cycle. The auto-incrementing address mode is useful to access a block of registers of incrementing addresses.

For example, to read the pace and ECG data registers located from address 0x30 to address 0x3F and worth 16 bytes of data, follow the next steps:

1. Execute a read command to address 0x30.
2. Extend the CSB assertion during 136 clock cycles (8+8*16).

During an auto-incrementing read access, SDO outputs the register contents every 8 clock cycles after the initial 8 clocks of the command field. During an auto-incrementing write access, the data is written to the registers every 8 clock cycles after the initial 8 clocks of the command field.

Automatic address increment stops at address 0x4F for both write and read operations.

8.5.6 Streaming

A read access cycle can operate in streaming mode, also referred to as loop read-back mode, by performing a read operation from the DATA_LOOP register and extending the CSB assertion beyond the standard 16 clocks. The streaming mode is supported for the DATA_STATUS, DATA_CH1_PACE, DATA_CH2_PACE, DATA_CH3_PACE, DATA_CH1_ECG, DATA_CH2_ECG and DATA_CH3_ECG registers described in Pace and ECG Data Read Back Registers. The streaming mode is useful to access the block of pace and ECG data registers when not all data needs to be read. The channels to read in this mode are selected in the CH_CNFG register. In this mode, CSB must be asserted during 8*(1+N) clock cycles, where N is the number source bytes enabled in CH_CNFG . The source for pace data is 2 bytes long; the source for ECG data is 3 bytes long, and the source for data status is 1 byte long.

For example, to read the DATA_STATUS, DATA_CH3_PACE and DATA_CH3_ECG registers located at address 0x30, 0x35 and 0x3D and worth 6 bytes of data, follow the next steps:

1. Write a value of 0x49 to the CH_CNFG register (address 0x2F).
2. Read from the DATA_LOOP register (address 0x50).
3. Extend the CSB assertion for 56 clock cycles (8+8*6).

8.5.7 Data Ready Bar

Data ready bar (DRDYB) is an active low-output signal and is asserted when new data is ready to be read. After DRDYB is asserted and an SPI read of ECG or PACE data occurs, DRDYB will be deasserted at the 14th rising edge of SCLK.

Figure 30. DRDYB Behavior for a Complete Read Operation

New data is available regardless of the serial interface being ready to read the data or not, and therefore, the data is lost if it is not read before the next DRDYB assertion. If DRDYB is asserted and the data is not read, DRDYB is automatically deasserted at least t_DRDYB seconds before the next DRDYB assertion. The value for t_DRDYB can be found in and .

Figure 31. DRDYB Behavior for an Incomplete Read Operation

The source channel driving the assertion of the DRDYB signal can be configured in the DRDYB_SRC register. In order to see the DRDYB output pin asserted, one bit of this register must be set to 1 to select the digital channel to drive it. Multiple channels should not be selected to drive the DRDYB output pin, otherwise, it will result in unexpected behavior. The selected channel should not be shut down in the AFE_SHDN_CN register, and if the source is an ECG channel, its filter should not be disabled in the DIS_EFILTER register. TI strongly recommends selecting the channel with the fastest data rate as the source for the DRDYB signal to avoid loss of data.

By default, the DRDYB signal is masked during the first few data samples after the start of a conversion or when a synchronization error is detected. If any ECG channel is enabled, DRDYB is masked during the first six data samples of the slowest enabled ECG channel. If all ECG channels are disabled, DRDYB is masked for the first six data samples of the slowest enabled pace channel when the data rate is 1xODR, and for the first eleven data samples of the slowest enabled pace channel when the data rate is 2xODR. Masking can be disabled in the MASK_DRDYB register.

8.5.8 Simultaneous ECG and Pace Data Read

Each of the three digital channels of the ADS1293 provides a high-performance path for ECG monitoring and a lower-resolution path for monitoring of pace-maker signals. The digitized signals from these two paths can be read simultaneously from the Pace and ECG Data Read Back Registers.

The ECG signal path achieves higher resolution than the PACE signal path by having one extra filtering stage (as shown in Sinc Filters). Due to the difference in filtering stages of the two paths, the PACE data is available for reading at a much higher rate than the ECG data. In this sense, the PACE channel must be selected as the driving source of the DRDYB signal.

In the Streaming mode, the data from the DATA_LOOP register should be read after the DRDYB line is asserted; this means that new data is available. In order to read both ECG and PACE data from the DATA_LOOP register, the channels of interest must be enabled in the CH_CNFG register.

As an example, the 3-Lead ECG Application can be reconfigured to perform simultaneous ECG and PACE data reads from channel 1:

1. Set address 0x00 = 0x00: Stops data conversion (if any).
2. Set address 0x2F = 0x32: Enables channel 1 PACE, channel 1 ECG, and channel 2 ECG for loop.
   read-back mode
3. Set address 0x27 = 0x01: Reconfigures the DRDYB source to channel 1 PACE .
4. Set address 0x00 = 0x01: Starts data conversion.

In this case, new PACE data from channel 1 is available on every DRDYB assertion; ECG data from channel 1 and channel 2, on the other hand, is available every six DRDYB assertions (R3_RATE_CH1 = R3_RATE_CH2 = 6).

There are different approaches for handling simultaneous ECG and PACE data read. One approach is to read ECG data every time that PACE data is ready, over-sampling the ECG channel. This is possible because old conversion values are retained in the data registers until new data overwrites them.

A second approach is to also read the DATA_STATUS register. Continuing from the steps above:

5. Set address 0x00 = 0x00: Stops data conversion.
6. Set address 0x2F = 0x33: Enables data ready status, channel 1 PACE, channel 1 ECG, and channel 2.
   ECG for loop read-back mode
7. Set address 0x00 = 0x01: Starts data conversion.

The DATA_STATUS register indicates the channel(s) that are updated at a given DRDYB assertion; this information can potentially be used to discard irrelevant data.

A third and more complex approach is to continuously reprogram the CH_CNFG register based on the contents of DATA_STATUS register. The CH_CNFG register should be reprogrammed to read PACE+ECG data only when the DATA_STATUS register indicates ECG data is available. After reading the PACE+ECG data, the CH_CNFG register should be reprogrammed back to reading only the DATA_STATUS register and the PACE data. In this case, the ECG data is not oversampled and the SPI communication can be significantly reduced for cases where a decimation rate, R3_RATE_CHx, is large. The reconfiguration of the CH_CNFG register should be done before the next DRDYB assertion to avoid losing data.

8.6.1 Operation Mode Registers

8.6.2 Input Channel Selection Registers

8.6.3 Lead-Off Detect Control Registers

8.6.4 Common-Mode Detection and Right-Leg Drive Common-Mode Feedback Control Registers

8.6.5 Wilson Control Registers

8.6.6 Reference Registers

8.6.7 OSC Control Registers

8.6.8 AFE Control Registers

8.6.9 Error Status Registers

8.6.10 Digital Registers

8.6.11 Pace and ECG Data Read Back Registers