米6体育平台手机版

ZHCS054C February 2011 – June 2017 ADS4122 , ADS4125 , ADS4142 , ADS4145

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND131R

订购信息

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.⁽¹⁾

		MIN	MAX	UNIT
Supply voltage, AVDD		–0.3	2.1	V
Supply voltage, DRVDD		–0.3	2.1	V
Voltage between AGND and DRGND		–0.3	0.3	V
Voltage between AVDD to DRVDD (when AVDD leads DRVDD)		0	2.1	V
Voltage between DRVDD to AVDD (when DRVDD leads AVDD)		0	2.1	V
Voltage applied to input pins	INP, INM	–0.3	minimum (1.9, AVDD + 0.3)	V
	CLKP, CLKM⁽²⁾, DFS, OE	–0.3	AVDD + 0.3
	RESET, SCLK, SDATA, SEN	–0.3	3.9
Operating free-air temperature, T_A		–40	85	°C
Operating junction temperature, T_J			125	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) When AVDD is turned off, it is recommended to switch off the input clock (or ensure the voltage on CLKP, CLKM is less than |0.3 V|. This prevents the ESD protection diodes at the clock input pins from turning on.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range, unless otherwise noted.

			MIN	NOM	MAX	UNIT
SUPPLIES
AVDD	Analog supply voltage		1.7	1.8	1.9	V
DRVDD	Digital supply voltage		1.7	1.8	1.9	V
ANALOG INPUTS
	Differential input voltage⁽¹⁾			2		V_PP
	Input common-mode voltage			V_CM ± 0.05		V
	Maximum analog input frequency with 2-V_PP input amplitude⁽²⁾			400		MHz
	Maximum analog input frequency with 1-V_PP input amplitude⁽²⁾			800		MHz
CLOCK INPUT
	Input clock sample rate	ADS4122, ADS4142, low-speed mode enabled by default	3		65	MSPS
		ADS4125, ADS4145, low-speed mode enabled	3		80
		ADS4125, ADS4145, low-speed mode disabled	> 80		125
	Input clock amplitude differential (V_CLKP – V_CLKM)	Sine wave, ac-coupled	0.2	1.5		V_PP
		LVPECL, ac-coupled		1.6
		LVDS, ac-coupled		0.7
		LVCMOS, single-ended, ac-coupled		1.8		V
	Input clock duty cycle	Low-speed enabled	40%	50%	60%
	Input clock duty cycle	Low-speed disabled	35%	50%	65%
DIGITAL OUTPUTS
C_LOAD	Maximum external load capacitance from each output pin to DRGND			5		pF
R_LOAD	Differential load resistance between the LVDS output pairs (LVDS mode)			100		Ω
T_A	Operating free-air temperature		–40		85	°C

(1) With 0-dB gain. See the Gain for SFDR, SNR Trade-Off section in the Application Information for the relationship between input voltage range and gain.

(2) See the Application Information section.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS412x, ADS414x	UNIT
		RGZ (VQFN)
		48 PIN
R_θJA	Junction-to-ambient thermal resistance	29	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	N/A	°C/W
R_θJB	Junction-to-board thermal resistance	10	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	9	°C/W
R_θJCbot	Junction-to-case (bottom) thermal resistance	1.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics: ADS412x

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, and DDR LVDS interface, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	Resolution					12	Bits
SNR	Signal-to-noise ratio, LVDS	f_IN = 10 MHz	ADS4122 (65 MSPS)		71.1		dBFS
		f_IN = 10 MHz	ADS4125 (125 MSPS)		71
		f_IN = 70 MHz	ADS4122 (65 MSPS)		70.9
		f_IN = 70 MHz	ADS4125 (125 MSPS)		70.8
		f_IN = 100 MHz	ADS4122 (65 MSPS)		70.7
		f_IN = 100 MHz	ADS4125 (125 MSPS)		70.6
		f_IN = 170 MHz	ADS4122 (65 MSPS)	67	70.2
		f_IN = 170 MHz	ADS4125 (125 MSPS)	68	70.1
		f_IN = 300 MHz	ADS4122 (65 MSPS)		68.8
		f_IN = 300 MHz	ADS4125 (125 MSPS)		69.6
SINAD	Signal-to-noise and distortion ratio, LVDS	f_IN = 10 MHz	ADS4122 (65 MSPS)		70.8		dBFS
		f_IN = 10 MHz	ADS4125 (125 MSPS)		70.7
		f_IN = 70 MHz	ADS4122 (65 MSPS)		70.8
		f_IN = 70 MHz	ADS4125 (125 MSPS)		70.7
		f_IN = 100 MHz	ADS4122 (65 MSPS)		70.6
		f_IN = 100 MHz	ADS4125 (125 MSPS)		70.3
		f_IN = 170 MHz	ADS4122 (65 MSPS)	66	70.1
		f_IN = 170 MHz	ADS4125 (125 MSPS)	67	69.8
		f_IN = 300 MHz	ADS4122 (65 MSPS)		68
		f_IN = 300 MHz	ADS4125 (125 MSPS)		69
SFDR	Spurious-free dynamic range	f_IN = 10 MHz	ADS4122 (65 MSPS)		86.5		dBc
		f_IN = 10 MHz	ADS4125 (125 MSPS)		86
		f_IN = 70 MHz			86
		f_IN = 100 MHz	ADS4122 (65 MSPS)		87
		f_IN = 100 MHz	ADS4125 (125 MSPS)		82
		f_IN = 170 MHz	ADS4122 (65 MSPS)	70	85
		f_IN = 170 MHz	ADS4125 (125 MSPS)	71	81
		f_IN = 300 MHz	ADS4122 (65 MSPS)		72.5
		f_IN = 300 MHz	ADS4125 (125 MSPS)		77
THD	Total harmonic distortion	f_IN = 10 MHz	ADS4122 (65 MSPS)		82.5		dBc
		f_IN = 10 MHz	ADS4125 (125 MSPS)		82
		f_IN = 70 MHz	ADS4122 (65 MSPS)		84
		f_IN = 70 MHz	ADS4125 (125 MSPS)		83.5
		f_IN = 100 MHz	ADS4122 (65 MSPS)		84
		f_IN = 100 MHz	ADS4125 (125 MSPS)		80.5
		f_IN = 170 MHz	ADS4122 (65 MSPS)	69.5	81
		f_IN = 170 MHz	ADS4125 (125 MSPS)	69.5	79.5
		f_IN = 300 MHz	ADS4122 (65 MSPS)		72
		f_IN = 300 MHz	ADS4125 (125 MSPS)		75.5
HD2	Second-order harmonic distortion	f_IN = 10 MHz			87		dBc
		f_IN = 70 MHz	ADS4122 (65 MSPS)		88
		f_IN = 70 MHz	ADS4125 (125 MSPS)		86
		f_IN = 100 MHz	ADS4122 (65 MSPS)		88
		f_IN = 100 MHz	ADS4125 (125 MSPS)		82
		f_IN = 170 MHz	ADS4122 (65 MSPS)	70	86
		f_IN = 170 MHz	ADS4125 (125 MSPS)	71	83
		f_IN = 300 MHz	ADS4122 (65 MSPS)		72.5
		f_IN = 300 MHz	ADS4125 (125 MSPS)		77
HD3	Third-order harmonic distortion	f_IN = 10 MHz	ADS4122 (65 MSPS)		86.5		dBc
		f_IN = 10 MHz	ADS4125 (125 MSPS)		86
		f_IN = 70 MHz	ADS4122 (65 MSPS)		86
		f_IN = 70 MHz	ADS4125 (125 MSPS)		88
		f_IN = 100 MHz	ADS4122 (65 MSPS)		87
		f_IN = 100 MHz	ADS4125 (125 MSPS)		85
		f_IN = 170 MHz	ADS4122 (65 MSPS)	70	85
		f_IN = 170 MHz	ADS4125 (125 MSPS)	71	81
		f_IN = 300 MHz	ADS4122 (65 MSPS)		85
		f_IN = 300 MHz	ADS4125 (125 MSPS)		82
	Worst spur (other than second and third harmonics)	f_IN = 10 MHz	ADS4122 (65 MSPS)		96		dBc
		f_IN = 10 MHz	ADS4125 (125 MSPS)		95
		f_IN = 70 MHz	ADS4122 (65 MSPS)		96
		f_IN = 70 MHz	ADS4125 (125 MSPS)		95
		f_IN = 100 MHz	ADS4122 (65 MSPS)		94
		f_IN = 100 MHz	ADS4125 (125 MSPS)		95
		f_IN = 170 MHz	ADS4122 (65 MSPS)	76.5	92
		f_IN = 170 MHz	ADS4125 (125 MSPS)	76.5	91
		f_IN = 300 MHz			88
IMD	Two-tone intermodulation distortion	f₁ = 100 MHz, f₂ = 105 MHz, each tone at –7 dBFS	ADS4122 (65 MSPS)		90		dBFS
IMD	Two-tone intermodulation distortion	f₁ = 100 MHz, f₂ = 105 MHz, each tone at –7 dBFS	ADS4125 (125 MSPS)		87.5		dBFS
	Input overload recovery	Recovery to within 1% (of final value) for 6-dB overload with sine-wave input			1		Clock cycles
PSRR	AC power-supply rejection ratio	For 100-mV_PP signal on AVDD supply, up to 10 MHz			> 30		dB
ENOB	Effective number of bits	f_IN = 170 MHz			11.2		LSBs
DNL	Differential nonlinearity	f_IN = 170 MHz		–0.85	±0.2	1.5	LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz	ADS4122 (65 MSPS)		±0.3	3.5	LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz	ADS4125 (125 MSPS)		±0.35	3.5	LSBs

7.6 Electrical Characteristics: ADS414x

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
	Resolution					14	Bits
SNR	Signal-to-noise ratio, LVDS	f_IN = 10 MHz	ADS4142 (65 MSPS)		73.9		dBFS
		f_IN = 10 MHz	ADS4145 (125 MSPS)		73.7
		f_IN = 70 MHz	ADS4142 (65 MSPS)		73.5
		f_IN = 70 MHz	ADS4145 (125 MSPS)		73.4
		f_IN = 100 MHz	ADS4142 (65 MSPS)		73.2
		f_IN = 100 MHz	ADS4145 (125 MSPS)		73.1
		f_IN = 170 MHz	ADS4142 (65 MSPS)	69	72.4
		f_IN = 170 MHz	ADS4145 (125 MSPS)	70	72.2
		f_IN = 300 MHz	ADS4142 (65 MSPS)		70.5
		f_IN = 300 MHz	ADS4145 (125 MSPS)		71.3
SINAD	Signal-to-noise and distortion ratio, LVDS	f_IN = 10 MHz	ADS4142 (65 MSPS)		73.5		dBFS
		f_IN = 10 MHz	ADS4145 (125 MSPS)		73.2
		f_IN = 70 MHz	ADS4142 (65 MSPS)		73.3
		f_IN = 70 MHz	ADS4145 (125 MSPS)		73
		f_IN = 100 MHz	ADS4142 (65 MSPS)		73
		f_IN = 100 MHz	ADS4145 (125 MSPS)		72.6
		f_IN = 170 MHz	ADS4142 (65 MSPS)	68	72.3
		f_IN = 170 MHz	ADS4145 (125 MSPS)	69	71.8
		f_IN = 300 MHz	ADS4142 (65 MSPS)		69.2
		f_IN = 300 MHz	ADS4145 (125 MSPS)		70.6
SFDR	Spurious-free dynamic range	f_IN = 10 MHz	ADS4142 (65 MSPS)		87		dBc
		f_IN = 10 MHz	ADS4145 (125 MSPS)		86
		f_IN = 70 MHz	ADS4142 (65 MSPS)		86.5
		f_IN = 70 MHz	ADS4145 (125 MSPS)		85.5
		f_IN = 100 MHz	ADS4142 (65 MSPS)		87
		f_IN = 100 MHz	ADS4145 (125 MSPS)		82
		f_IN = 170 MHz	ADS4142 (65 MSPS)	71	85
		f_IN = 170 MHz	ADS4145 (125 MSPS)	72.5	81.5
		f_IN = 300 MHz	ADS4142 (65 MSPS)		72.5
		f_IN = 300 MHz	ADS4145 (125 MSPS)		77
THD	Total harmonic distortion	f_IN = 10 MHz	ADS4142 (65 MSPS)		84		dBc
		f_IN = 10 MHz	ADS4145 (125 MSPS)		83
		f_IN = 70 MHz	ADS4142 (65 MSPS)		84
		f_IN = 70 MHz	ADS4145 (125 MSPS)		83.5
		f_IN = 100 MHz	ADS4142 (65 MSPS)		84
		f_IN = 100 MHz	ADS4145 (125 MSPS)		81
		f_IN = 170 MHz	ADS4142 (65 MSPS)	69.5	82.5
		f_IN = 170 MHz	ADS4145 (125 MSPS)	70.5	80
		f_IN = 300 MHz	ADS4142 (65 MSPS)		72.5
		f_IN = 300 MHz	ADS4145 (125 MSPS)		75.5
HD2	Second-order harmonic distortion	f_IN = 10 MHz	ADS4142 (65 MSPS)		88		dBc
		f_IN = 10 MHz	ADS4145 (125 MSPS)		87
		f_IN = 70 MHz	ADS4142 (65 MSPS)		87
		f_IN = 70 MHz	ADS4145 (125 MSPS)		85.5
		f_IN = 100 MHz	ADS4142 (65 MSPS)		88
		f_IN = 100 MHz	ADS4145 (125 MSPS)		82
		f_IN = 170 MHz	ADS4142 (65 MSPS)	71	87
		f_IN = 170 MHz	ADS4145 (125 MSPS)	72.5	84
		f_IN = 300 MHz	ADS4142 (65 MSPS)		72.5
		f_IN = 300 MHz	ADS4145 (125 MSPS)		77
HD3	Third-order harmonic distortion	f_IN = 10 MHz	ADS4142 (65 MSPS)		87		dBc
		f_IN = 10 MHz	ADS4145 (125 MSPS)		86
		f_IN = 70 MHz	ADS4142 (65 MSPS)		86.5
		f_IN = 70 MHz	ADS4145 (125 MSPS)		87
		f_IN = 100 MHz	ADS4142 (65 MSPS)		87
		f_IN = 100 MHz	ADS4145 (125 MSPS)		85
		f_IN = 170 MHz	ADS4142 (65 MSPS)	71	85
		f_IN = 170 MHz	ADS4145 (125 MSPS)	72.5	81.5
		f_IN = 300 MHz	ADS4142 (65 MSPS)		85
		f_IN = 300 MHz	ADS4145 (125 MSPS)		84
	Worst spur (other than second and third harmonics)	f_IN = 10 MHz	ADS4142 (65 MSPS)		96		dBc
		f_IN = 10 MHz	ADS4145 (125 MSPS)		95
		f_IN = 70 MHz			95
		f_IN = 100 MHz	ADS4142 (65 MSPS)		94
		f_IN = 100 MHz	ADS4145 (125 MSPS)		95
		f_IN = 170 MHz	ADS4142 (65 MSPS)	77.5	92
		f_IN = 170 MHz	ADS4145 (125 MSPS)	78.5	91
		f_IN = 300 MHz	ADS4142 (65 MSPS)		87
		f_IN = 300 MHz	ADS4145 (125 MSPS)		88
IMD	Two-tone intermodulation distortion	f₁ = 100 MHz, f₂ = 105 MHz, each tone at –7 dBFS	ADS4142 (65 MSPS)		88.5		dBFS
IMD	Two-tone intermodulation distortion	f₁ = 100 MHz, f₂ = 105 MHz, each tone at –7 dBFS	ADS4145 (125 MSPS)		87.5		dBFS
	Input overload recovery	Recovery to within 1% (of final value) for 6-dB overload with sine-wave input			1		Clock cycles
PSRR	AC power-supply rejection ratio	For 100-mV_PP signal on AVDD supply, up to 10 MHz			> 30		dB
ENOB	Effective number of bits	f_IN = 170 MHz	ADS4142 (65 MSPS)		11.5		LSBs
ENOB	Effective number of bits	f_IN = 170 MHz	ADS4145 (125 MSPS)		11.3		LSBs
DNL	Differential nonlinearity	f_IN = 170 MHz		–0.95	±0.5	1.7	LSBs
INL	Integrated nonlinearity	f_IN = 170 MHz			±1.5	±4.5	LSBs

7.7 Electrical Characteristics: General

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, 50% clock duty cycle, and 0-dB gain, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Differential input voltage			2		V_PP
	Differential input resistance	At dc, see Figure 106		> 1		MΩ
	Differential input capacitance	See Figure 107		4		pF
	Analog input bandwidth			550		MHz
	Analog input common-mode current (per input pin)			0.6		µA/MSPS
VCM	Common-mode output voltage			0.95		V
	VCM output current capability			4		mA
DC ACCURACY
	Offset error		–15	2.5	15	mV
	Temperature coefficient of offset error			0.003		mV/°C
E_GREF	Gain error as a result of internal reference inaccuracy alone		–2		2	%FS
E_GCHAN	Gain error of channel alone			–0.2		%FS
	Temperature coefficient of E_GCHAN			0.001		Δ%/°C
POWER SUPPLY
IAVDD	Analog supply current	ADS4122, ADS4142 (65 MSPS)		42	55	mA
IAVDD	Analog supply current	ADS4125, ADS4145 (125 MSPS)		62	75	mA
IDRVDD⁽²⁾	Output buffer supply current, LVDS interface with 100-Ω external termination, low LVDS swing (200 mV)	ADS4122, ADS4142 (65 MSPS)		28.5		mA
		ADS4125, ADS4145 (125 MSPS)		35.5
	Output buffer supply current, LVDS interface with 100-Ω external termination, standard LVDS swing (350 mV)	ADS4122, ADS4142 (65 MSPS)		40	53
		ADS4125, ADS4145 (125 MSPS)		48	57
	Output buffer supply current⁽²⁾⁽¹⁾, CMOS interface⁽¹⁾, 8-pF external load capacitance, f_IN = 2.5 MHz	ADS4122, ADS4142 (65 MSPS)		15
		ADS4125, ADS4145 (125 MSPS)		23
	Analog power	ADS4122, ADS4142 (65 MSPS)		76		mW
	Analog power	ADS4122, ADS4142 (125 MSPS)		112		mW
	Digital power, LVDS interface, low LVDS swing	ADS4122, ADS4142 (65 MSPS)		52		mW
	Digital power, LVDS interface, low LVDS swing	ADS4122, ADS4142 (125 MSPS)		66.5		mW
	Digital power, CMOS interface⁽¹⁾, 8-pF external load capacitance, f_IN = 2.5 MHz	ADS4122, ADS4142 (65 MSPS)		27		mW
		ADS4122, ADS4142 (125 MSPS)		41.5		mW
	Global power-down			10	15	mW
	Standby	ADS4122, ADS4142 (65 MSPS)		105		mW
	Standby	ADS4122, ADS4142 (125 MSPS)		130		mW

(1) In CMOS mode, the DRVDD current scales with the sampling frequency, the load capacitance on output pins, input frequency, and the supply voltage (see the CMOS Interface Power Dissipation section in the Application Information).

(2) The maximum DRVDD current with CMOS interface depends on the actual load capacitance on the digital output lines. Note that the maximum recommended load capacitance on each digital output line is 10 pF.

7.8 Digital Characteristics

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, and 50% clock duty cycle for the ADS4122, ADS4125, ADS4142, and ADS4145, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, OE)
High-level input voltage		RESET, SCLK, SDATA, and SEN support 1.8-V and 3.3-V CMOS logic levels	1.3			V
Low-level input voltage					0.4	V
High-level input voltage		OE only supports 1.8-V CMOS logic levels	1.3			V
Low-level input voltage		OE only supports 1.8-V CMOS logic levels			0.4	V
High-level input current: SDATA, SCLK⁽¹⁾		V_HIGH = 1.8 V		10		µA
High-level input current: SEN		V_HIGH = 1.8 V		0		µA
Low-level input current: SDATA, SCLK		V_LOW = 0 V		0		µA
Low-level input current: SEN		V_LOW = 0 V		–10		µA
DIGITAL OUTPUTS (CMOS INTERFACE: D0 TO D13, OVR_SDOUT)
High-level output voltage			DRVDD – 0.1	DRVDD		V
Low-level output voltage				0	0.1	V
DIGITAL OUTPUTS (LVDS INTERFACE: DA0P/M TO DA13P/M, DB0P/M TO DB13P/M, CLKOUTP/M)
High-level output voltage⁽²⁾	V_ODH	Standard swing LVDS	270	350	430	mV
Low-level output voltage⁽²⁾	V_ODL	Standard swing LVDS	–430	–350	–270	mV
High-level output voltage⁽²⁾	V_ODH	Low swing LVDS		200		mV
Low-level output voltage⁽²⁾	V_ODL	Low swing LVDS		–200		mV
Output common-mode voltage	V_OCM		0.85	1.05	1.25	V

(1) SDATA and SCLK have an internal 180-kΩ pull-down resistor.

(2) With an external 100-Ω termination.

7.9 Timing Requirements: LVDS and CMOS Modes⁽¹⁾

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 125 MSPS, sine wave input clock, C_LOAD = 5 pF⁽²⁾, and R_LOAD = 100 Ω⁽³⁾, unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.

			MIN	TYP	MAX	UNIT
GENERAL
t_A	Aperture delay		0.6	0.8	1.2	ns
	Variation of aperture delay between two devices at the same temperature and DRVDD supply			±100		ps
t_J	Aperture jitter			100		f_S rms
	Wakeup time:	Time to valid data after coming out of STANDBY mode		5	25	µs
	Wakeup time:	Time to valid data after coming out of PDN GLOBAL mode		100	500	µs
	ADC latency⁽⁴⁾:	Low-latency mode (default after reset)		10		Clock cycles
		Low-latency mode disabled (gain enabled, offset correction disabled)		16		Clock cycles
		Low-latency mode disabled (gain and offset correction enabled)		17		Clock cycles
DDR LVDS MODE⁽⁵⁾⁽⁶⁾
t_SU	Data setup time⁽³⁾: data valid⁽⁷⁾ to zero-crossing of CLKOUTP		2.3	3		ns
t_H	Data hold time⁽³⁾: zero-crossing of CLKOUTP to data becoming invalid⁽⁷⁾		0.35	0.6		ns
t_PDI	Clock propagation delay: input clock rising edge cross-over to output clock rising edge cross-over, sampling frequency ≤ 125 MSPS		3	4.2	5.4	ns
	Variation of t_PDI between two devices at the same temperature and DRVDD supply			±0.6		ns
	LVDS bit clock duty cycle of differential clock, (CLKOUTP – CLKOUTM), sampling frequency ≤ 125 MSPS			48%
t_RISE, t_FALL	Data rise time, data fall time: rise time measured from –100 mV to 100 mV, fall time measured from 100 mV to –100 mV, sampling frequency ≤ 125 MSPS			0.14		ns
t_CLKRISE, t_CLKFALL	Output clock rise time, output clock fall time rise time measured from –100 mV to 100 mV, fall time measured from 100 mV to –100 mV, sampling frequency ≤ 125 MSPS			0.14		ns
t_OE	Output enable (OE) to data delay: time to valid data after OE becomes active			50	100	ns
PARALLEL CMOS MODE⁽⁸⁾
t_SETUP	Data setup time: data valid⁽⁹⁾ to 50% of CLKOUT rising edge		3.1	3.7		ns
t_HOLD	Data hold time: 50% of of CLKOUT rising edge to data becoming invalid⁽⁹⁾		3.2	4		ns
t_PDI	Clock propagation delay: input clock rising edge cross-over to 50% of output clock rising edge, sampling frequency ≤ 125 MSPS		4	5.5	7	ns
	Output clock duty cycle of output clock, CLKOUT, sampling frequency ≤ 125 MSPS			47%
t_RISE, t_FALL	Data rise time, data fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, sampling frequency ≤ 125 MSPS			0.35		ns
t_CLKRISE, t_CLKFALL	Output clock rise time, output clock fall time: rise time measured from 20% to 80% of DRVDD, fall time measured from 80% to 20% of DRVDD, sampling frequency ≤ 125 MSPS			0.35		ns
t_OE	Output enable (OE) to data delay: time to valid data after OE becomes active			20	40	ns

(1) Timing parameters are ensured by design and characterization but are not production tested.

(2) C_LOAD is the effective external single-ended load capacitance between each output pin and ground.

(3) R_LOAD is the differential load resistance between the LVDS output pair.

(4) At higher frequencies, t_PDI is greater than one clock period and overall latency = ADC latency + 1.

(5) Measurements are done with a transmission line of 100-Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.

(6) The LVDS timings are unchanged for low latency disabled and enabled.

(7) Data valid refers to a logic high of 100 mV and a logic low of –100 mV.

(8) Low latency mode enabled.

(9) Data valid refers to a logic high of 1.25 V and a logic low of 0.54 V.

7.10 Serial Interface Timing Characteristics

Typical values at 25°C, minimum and maximum values across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V, unless otherwise noted.

PARAMETER		MIN	MAX	UNIT
f_SCLK	SCLK frequency (equal to 1/t_SCLK)	> dc	20	MHz
t_SLOADS	SEN to SCLK setup time	25		ns
t_SLOADH	SCLK to SEN hold time	25		ns
t_DSU	SDATA setup time	25		ns
t_DH	SDATA hold time	25		ns

7.11 Reset Timing Requirements

Typical values at 25°C and minimum and maximum values across the full temperature range: T_MIN = –40°C to T_MAX = 85°C, unless otherwise noted.

		MIN	MAX	UNIT
t₁	Power-on delay from power-up of AVDD and DRVDD to RESET pulse active	1		ms
t₂	Reset pulse duration of active RESET signal that resets the serial registers	10		ns
t₂			1⁽¹⁾	µs
t₃	Delay from RESET disable to SEN active	100		ns

(1) The reset pulse is needed only when using the serial interface configuration. If the pulse width is greater than 1µs, the device could enter the parallel configuration mode briefly and then return back to serial interface mode.

7.12 Timing Characteristics at Lower Sampling Frequencies

SAMPLING FREQUENCY (MSPS)	t_su, SETUP TIME			t_h, HOLD TIME			t_PDI, CLOCK PROPAGATION DELAY			UNIT
SAMPLING FREQUENCY (MSPS)	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
DDR LVDS										ns
65	5.5	6.5		0.35	0.6					ns
80	4.5	5.2		0.35	0.6					ns
CMOS (LOW LATENCY ENABLED)⁽¹⁾										ns
65	6.5	7.5		6.5	7.5		4	5.5	7	ns
80	5.4	6		5.4	6		4	5.5	7	ns
CMOS (LOW LATENCY DISABLED)⁽¹⁾										ns
65	6	7		7	8		4	5.5	7	ns
80	4.8	5.5		5.7	6.5		4	5.5	7	ns
125	2.5	3.2		3.5	4.3		4	5.5	7	ns

(1) Timing specified with respect to output clock

ADS4122 ADS4125 ADS4142 ADS4145 tim_lvds_vo_level_bas483.gif

NOINDENT:

With external 100-Ω termination.

Figure 1. LVDS Output Voltage Levels

ADS4122 ADS4125 ADS4142 ADS4145 tim_latency_mode_bas483.gif

NOINDENT:

ADC latency in low-latency mode. At higher sampling frequencies, t_DPI is greater than one clock cycle which then makes the overall latency = ADC latency + 1.

NOINDENT:

E = Even bits (D0, D2, D4, and so forth). O = Odd bits (D1, D3, D5, and so forth).

Figure 2. Latency Diagram

ADS4122 ADS4125 ADS4142 ADS4145 tim_lvds_mode_bas483.gif

NOINDENT:

Dn = bits D0, D2, D4, and so forth. Dn + 1 = Bits D1, D3, D5, and so forth.

Figure 3. LVDS Mode Timing

ADS4122 ADS4125 ADS4142 ADS4145 tim_latency_bas483.gif

NOINDENT:

Dn = bits D0, D1, D2, and so forth.

Figure 4. CMOS Mode Timing

ADS4122 ADS4125 ADS4142 ADS4145 tim_serial_iface_bas483.gif

Figure 5. Serial Interface Timing

ADS4122 ADS4125 ADS4142 ADS4145 tim_reset_bas483.gif

NOINDENT:

A high pulse on the RESET pin is required in the serial interface mode in case of initialization through hardware reset. For parallel interface operation, RESET must be permanently tied high.

Figure 6. Reset Timing Diagram

7.13 Typical Characteristics: ADS4122

At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_fft_20m_bas520.png

Figure 7. FFT for 20-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_fft_300m_bas520.png

Figure 9. FFT for 300-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_2tone_36amp_bas520.png

Figure 11. FFT for Two-Tone Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_snr-fin_bas520.png

Figure 13. SNR vs Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_sinad-g_fin_bas520.png

Figure 15. SINAD Across Gain and Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_perf-inamp_1tone_150m_bas520.png

Figure 17. Performance Across Input Amplitude
(Single Tone)

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_sfdr-tmp_avdd_bas520.png

Figure 19. SFDR Across Temperature vs AVDD Supply

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_perf-drvdd_bas520.png

Figure 21. Performance Across DRVDD Supply Voltage

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_perf-inamp_150m_bas520.png

Figure 23. Performance Across Input Clock Amplitude

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_fft_170m_bas520.png

Figure 8. FFT for 170-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_2tone_7amp_bas520.png

Figure 10. FFT for Two-Tone Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_sfdr-fin_bas520.png

Figure 12. SFDR vs Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_sfdr-g_fin_bas520.png

Figure 14. SFDR Across Gain and Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_perf-inamp_1tone_40m_bas520.png

Figure 16. Performance Across Input Amplitude
(Single Tone)

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_perf-vcm_bas520.png

Figure 18. Performance vs Input Common-Mode Voltage

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_snr-tmp_avdd_bas520.png

Figure 20. SNR Across Temperature vs AVDD Supply

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_perf-inamp_40m_bas520.png

Figure 22. Performance Across Input Clock Amplitude

ADS4122 ADS4125 ADS4142 ADS4145 tc_4122_snr-clk_dcy_bas520.png

Figure 24. Performance Across Input Clock Duty Cycle

7.14 Typical Characteristics: ADS4125

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_fft_20m_bas520.png

Figure 25. FFT for 20-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_fft_300m_bas520.png

Figure 27. FFT for 300-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_2tone_36amp_bas520.png

Figure 29. FFT for Two-Tone Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_snr-fin_bas520.png

Figure 31. SNR vs Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_sinad-g_fin_bas520.png

Figure 33. SINAD Across Gain and Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_perf-inamp_1tone_150m_bas520.png

Figure 35. Performance Across Input Amplitude
(Single Tone)

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_sfdr-tmp_avdd_bas520.png

Figure 37. SFDR Across Temperature vs AVDD Supply

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_perf-drvdd_bas520.png

Figure 39. Performance Across DRVDD Supply Voltage

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_perf-inamp_150m_bas520.png

Figure 41. Performance Across Input Clock Amplitude

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_fft_170m_bas520.png

Figure 26. FFT for 170-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_2tone_7amp_bas520.png

Figure 28. FFT for Two-Tone Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_sfdr-fin_bas520.png

Figure 30. SFDR vs Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_sfdr-g_fin_bas520.png

Figure 32. SFDR Across Gain and Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_perf-inamp_1tone_40m_bas520.png

Figure 34. Performance Across Input Amplitude
(Single Tone)

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_perf-vcm_bas520.png

Figure 36. Performance vs Input Common-Mode Voltage

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_snr-tmp_avdd_bas520.png

Figure 38. SNR Across Temperature vs AVDD Supply

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_perf-inamp_40m_bas520.png

Figure 40. Performance Across Input Clock Amplitude

ADS4122 ADS4125 ADS4142 ADS4145 tc_4125_snr-clk_dcy_bas520.png

Figure 42. SNR Across Input Clock Duty Cycle

7.15 Typical Characteristics: ADS4142

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_fft_20m_bas520.png

Figure 43. FFT for 20-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_fft_300m_bas520.png

Figure 45. FFT for 300-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_2tone_36amp_bas520.png

Figure 47. FFT for Two-Tone Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_snr-fin_bas520.png

Figure 49. SNR vs Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_sinad-g_fin_bas520.png

Figure 51. SINAD Across Gain and Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-inamp_150m_bas520.png

Figure 53. Performance Across Input Amplitude
(Single Tone)

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_sfdr-tmp_avdd_bas520.png

Figure 55. SFDR Across Temperature vs AVDD Supply

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-drvdd_bas520.png

Figure 57. Performance Across DRVDD Supply Voltage

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-dif_clk_150m_bas520.png

Figure 59. Performance Across Input Clock Amplitude

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_inl_bas520.png

Figure 61. Integral Nonlinearity

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_fft_170m_bas520.png

Figure 44. FFT for 170-MHz Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_2tone_7amp_bas520.png

Figure 46. FFT for Two-Tone Input Signal

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_sfdr-fin_bas520.png

Figure 48. SFDR vs Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_sfdr-g_fin_bas520.png

Figure 50. SFDR Across Gain and Input Frequency

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-inamp_40m_bas520.png

Figure 52. Performance Across Input Amplitude
(Single Tone)

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-vcm_bas520.png

Figure 54. Performance vs Input Common-Mode Voltage

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_snr-tmp_avdd_bas520.png

Figure 56. SNR Across Temperature vs AVDD Supply

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-dif_clk_40m_bas520.png

Figure 58. Performance Across Input Clock Amplitude

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_perf-clk_dcy_bas520.png

Figure 60. Performance Across Input Clock Duty Cycle

ADS4122 ADS4125 ADS4142 ADS4145 tc_4142_histo_noise_bas520.gif

Figure 62. Output Noise Histogram
(With Inputs Shorted to VCM)

7.16 Typical Characteristics: ADS4145

At 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum-rated sampling frequency, sine-wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1-dBFS differential analog input, 0-dB gain, low-latency mode, DDR LVDS output interface, and 32k-point FFT, unless otherwise noted.