8.3.4 Device Synchronization Using TX_TRIG

The device has multiple PLLs and clock dividers that are used to generate the programmable ADC resolutions and LVDS synchronization factors as well as to synchronize LVDS test patterns.

The TX_TRIG input is used to synchronize clock dividers inside the device. The synchronization achieved using TX_TRIG also enables multiple parallel devices to operate synchronously.

For the 32-input mode, the same ADC alternates between converting two inputs. The TX_TRIG signal provides the mechanism to determine the sampling instants of the odd and even input signals with respect to the system clock, as shown in Figure 60.

Figure 60. Odd- and Even-Channel Sampling Instant Definition Mechanism in
32-Input Mode with the TX_TRIG Signal

For the 8-input mode, the conversion clock is obtained by dividing the system clock by 2. The phase of the division is again determined by the TX_TRIG signal, as shown in Figure 61.

Figure 61. Conversion Clock Deriving Mechanism from Division of the Sampling Clock in 8-Input Mode

Applying a pulse on TX_TRIG is a mandatory part of the power-up and initialization sequence; see the Power Sequencing and Initialization section.

In case a TX_TRIG is not applied, the device can possibly behave in an unexpected manner. The identified cases are shown in Table 6.

The TX_TRIG pulse resets the phase of the test pattern generator, the odd and even sampling phase selection, and the phase of the frame clock. As a result of this phase reset operation, the ADC data can be corrupted for four to six clocks immediately after applying TX_TRIG. The phase reset from TX_TRIG can be disabled using MASK_TX_TRIG.