ZHCSDS3C May 2015 – April 2018 ADS52J90
PRODUCTION DATA.
In order to achieve deterministic latency across the entire link, the device supports system-level link synchronization using the SYNC~ (in subclass 2) and SYSREF (in subclass 1) signals, as mentioned in the JESD204B standards document. The mapping of these signals to the pin voltages is shown in Table 26.
| SIGNAL NOTATION IN JESD204B DOCUMENT | RELATION TO DEVICE PINS |
|---|---|
| Device clock | ADC_CLKP – ADC_CLKM |
| SYNC~ | SYNCP_SERDES – SYNCM_SERDES |
| SYSREF(1) | SYSREFP_SERDES – SYSREFM_SERDES |
JESD subclasses 1 and 2 use an internal clock called the local multiframe clock (LMFC) to achieve deterministic latency in the link. The phase of the LMFC clock is set based on the device clock rising edge that the SYSREF (in subclass 1) or SYNC~(in subclass 2) signals are sampled on. The device clock is the highest speed input clock for the device and there is no provision for a higher speed adjustment clock to achieve phase adjustments finer than what is achievable using the device clock. By default, the LMFC count is reset to 0 during a SYNC~ or SYSREF event. This reset count can be forced to a different value by using the FORCE_LMFC_COUNT and LMFC_COUNTER_INIT_VALUE register controls. The LMFC does not exist in JESD subclass 0.
SYSREF can be a periodic, one-shot, or gapped periodic active-high signal that is sampled on the rising edge of the device clock. There is no option to sample the SYSREF signal on the falling edge of the device clock. If SYSREF is a periodic or gapped periodic signal, then its periodicity must be a multiple of the LMFC period in order to avoid unwanted sudden shifts in the phase of the LMFC. Note that a continuous periodic SYSREF can cause spurious degradation in the ADC performance because of energy coupling into the device at a rate that is a sub-harmonic of the device clock rate.
In addition to resetting the phase of the LMFC, SYSREF (or SYNC~) also resets some of the other internal clock dividers not related to the JESD block and affects the reset of the phase of the test pattern generator (see the LVDS Test Pattern Mode section). SYSREF (or SYNC~) also affects the reset of the frame clock phases and the odd or even sampling selection in 32-channel mode.
The default mode is to reset all internal dividers as well as the phase of the LMFC during every SYSREF (or SYNC~) event based on the JESD subclass.
The reset operations based on SYNC~ and SYSREF for the different subclasses occurs as shown in Table 27.
| SUBCLASS | EVENT CONTROLLING THE RESET | What gets reset | |
|---|---|---|---|
| JESD BLOCK (Phase of the LMFC Clock) | REST OF DEVICE | ||
| JESD204B-subclass 0 | SYNC~ rising edge | Not applicable | Yes |
| JESD204B-subclass 1 | SYSREF(1) | Yes | Yes |
| JESD204B-subclass 2 | SYNC~ rising edge | Yes | Yes |
| JESD204A | SYNC~ rising edge | Not applicable | Yes |
Table 28 lists the register controls to selectively mask the reset operations of the various blocks.
| REGISTER BIT | MASKS RESET OPERATION IN | ||
|---|---|---|---|
| JESD BLOCK (Phase of the LMFC Clock) | CLOCK DIVIDERS | OTHER SYNCHRONIZATION(1) | |
| JESD_RESET1 | No | Yes | Yes |
| JESD_RESET2 | Yes | Yes | No |
The JESD_RESET1 and JESD_RESET2 bits mask the reset operations as indicated in Table 28 for all subsequent SYNC~ and SYSREF events after the bits are set. The JESD_RESET3 register bit is functionally similar to JESD_RESET2 (in terms of masking the reset function to the blocks). However, when JESD_RESET3 is set, this bit allows the first SYNC~ or SYSREF event to reset all clock dividers, takes affect, and masks the reset of the LMFC clock divider only after the first SYNC~ or SYSREF event occurs. The JESD_RESET1, JESD_RESET2, and JESD_RESET3 bits can be used appropriately to avoid unwanted reset operations resulting from SYNC~ and SYSREF events.
When SYSREF resets the rest of the device, the ADC data can be corrupted for four to six clocks. If SYSREF is periodic, then periodic corruption of ADC data can result. Thus, when using a periodic or a gapped periodic SYSREF, one JESD_RESET (JESD_RESET1, JESD_RESET2, or JESD_RESET3) must be set to 1.