Figure 9-6 shows a histogram of output codes for when no signal is applied at the analog inputs of the ADS54J40 . Figure 9-7 shows that when the dc offset correction block of the device is bypassed, the output code histogram becomes multi-modal with as many as four peaks because the ADS54J40 is a 4-way interleaved ADC with each ADC core having a different internal dc offset.

Figure 9-6 Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is On)

Figure 9-7 Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is Off)

Figure 9-8 shows that when the dc offset correction block is frozen (instead of bypassed), the output code histogram improves (compared to when bypassed). However, when the temperature changes, the dc offset difference among interleaving cores may increase resulting in increased spacing between peaks in the histogram.

Figure 9-8 Idle Channel Histogram (No Signal at Analog Inputs, DC Offset Correction is Frozen)