The ADS54J40 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high impedance input across a very wide frequency range to the external driving source that enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, resulting in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to VCM using 600-Ω resistors, allowing for ac-coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM +
0.475 V) and (VCM – 0.475 V), resulting in a 1.9-V_PP (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 1.2 GHz. An equivalent analog input network diagram is shown in Figure 8-1.

Figure 8-1 Analog Input Network

The input bandwidth shown in Figure 8-2 is measured with respect to a 50-Ω differential input termination at the ADC input pins. Figure x shows the signal processing done inside the DDC block of the ADS54J40.

Figure 8-2 Transfer Function vs Frequency