The SYSREF signal is a periodic signal that is sampled by the ADS54J40 device clock and used to align the boundary of the local multi-frame clock inside the data converter. SYSREF is required to be a sub-harmonic of the local multiframe clock (LMFC) internal timing. To meet this requirement, the timing of SYSREF is dependent on the device clock frequency and the LMFC frequency, as determined by the selected DDC decimation and frames per multi-frame settings. The SYSREF signal is recommended to be a low-frequency signal in the range of 1 MHz to 5 MHz to reduce coupling to the signal path both on the printed circuit board (PCB) as well as internal in the device.

The external SYSREF signal must be a sub-harmonic of the internal LMFC clock, as shown in Equation 1 and Table 8-4.

where

• N = 0, 1, 2, and so forth.

For example, if LMFS = 8224 then the programmed value of K is 9 (the actual value is 9 + 1 = 10 because the actual value for K = the value set in the SPI register +1). If the device clock frequency is f_S = 1000 MSPS, then the local multi-frame clock frequency becomes (1000 / 4) / 10 = 25 MHz. The SYSREF signal frequency can be chosen as the LMFC frequency / 8 = 3.125 MHz.