ZHCSEE2B December 2015 – January 2023 ADS54J66
PRODUCTION DATA
The ADS54J66 provides a highly-configurable power-down mode. Power-down can be enabled using the PDN pin or SPI register writes.
A power-down mask can be configured that allows a trade-off between wake-up time and power consumption in power-down mode. Two independent power-down masks can be configured: MASK 1 and MASK 2, as shown in Table 7-9. See the master page registers in Table 7-15 for further details.
| REGISTER ADDRESS A[7:0] (Hex) | COMMENT | REGISTER DATA | |||||||
|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| MASTER PAGE (80h) | |||||||||
| 20 | MASK 1 | PDN ADC CHAB | PDN ADC CHCD | ||||||
| 21 | PDN BUFFER CHCD | PDN BUFFER CHAB | 0 | 0 | 0 | 0 | |||
| 23 | MASK 2 | PDN ADC CHAB | PDN ADC CHCD | ||||||
| 24 | PDN BUFFER CHCD | PDN BUFFER CHAB | 0 | 0 | 0 | 0 | |||
| 26 | CONFIG | GLOBAL PDN | OVERRIDE PDN PIN | PDN MASK SEL | 0 | 0 | 0 | 0 | 0 |
| 53 | 0 | MASK SYSREF | 0 | 0 | 0 | 0 | 0 | 0 | |
| 55 | 0 | 0 | 0 | PDN MASK | 0 | 0 | 0 | 0 | |
To save power, the device can be put in complete power down by using the GLOBAL PDN register bit. However, when JESD link must remain up when putting the device in power down, the ADC and analog buffer can be powered down by using the PDN ADC CHx and PDN BUFFER CHx register bits after enabling the PDN MASK register bit. The PDN MASK SEL register bit can be used to select between MASK 1 or MASK 2. Table 7-10 shows power consumption for different combinations of the GLOBAL PDN, PDN ADC CHx, and PDN BUFF CHx register bits.
| REGISTER BIT | COMMENT | IAVDD3V (mA) | IAVDD (mA) | IDVDD (mA) | IIOVDD (mA) | TOTAL POWER (W) |
|---|---|---|---|---|---|---|
| Default | After reset, with a full-scale input signal to both channels | 0.340 | 0.365 | 0.184 | 0.533 | 2.675 |
| GBL PDN = 1 | The device is in complete power-down state | 0.002 | 0.006 | 0.012 | 0.181 | 0.247 |
| GBL PDN = 0, PDN ADC CHx = 1 (x = AB or CD) | The ADCs of one pair of channels are powered down | 0.277 | 0.225 | 0.123 | 0.496 | 2.063 |
| GBL PDN = 0, PDN BUFF CHx = 1 (x = AB or CD) | The input buffers of one pair of channels are powered down | 0.266 | 0.361 | 0.187 | 0.527 | 2.445 |
| GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = AB or CD) | The ADCs and input buffers of one pair of channels are powered down | 0.200 | 0.224 | 0.126 | 0.492 | 1.830 |
| GBL PDN = 0, PDN ADC CHx = 1, PDN BUFF CHx = 1 (x = AB and CD) | The ADCs and input buffers of all channels are powered down | 0.060 | 0.080 | 0.060 | 0.448 | 0.960 |