SBAS404D October   2006  – February 2016 ADS8556 , ADS8557 , ADS8558

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: General
    6. 6.6  Electrical Characteristics: ADS8556
    7. 6.7  Electrical Characteristics: ADS8557
    8. 6.8  Electrical Characteristics: ADS8558
    9. 6.9  Power Dissipation Characteristics
    10. 6.10 Serial Interface Timing Requirements
    11. 6.11 Parallel Interface Timing Requirements (Read Access)
    12. 6.12 Parallel Interface Timing Requirements (Write Access)
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog
        1. 7.3.1.1 Analog Inputs
        2. 7.3.1.2 Analog-to-Digital Converter (ADC)
        3. 7.3.1.3 Conversion Clock
        4. 7.3.1.4 CONVST_x
        5. 7.3.1.5 BUSY/INT
        6. 7.3.1.6 Reference
      2. 7.3.2 Digital
        1. 7.3.2.1 Device Configuration
        2. 7.3.2.2 Parallel Interface
        3. 7.3.2.3 Serial Interface
        4. 7.3.2.4 Output Data Format
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Mode
      2. 7.4.2 Software Mode
      3. 7.4.3 Daisy-Chain Mode (in Serial Mode Only)
      4. 7.4.4 Sequential Mode (in Software Mode with External Conversion Clock Only)
      5. 7.4.5 Reset and Power-Down Modes
    5. 7.5 Register Maps
      1. 7.5.1 Control Register (CR); Default Value = 0x000003FF
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

5 Pin Configuration and Functions

PM Package
64-Pin LQFP
Top View
ADS8556 ADS8557 ADS8558 po_bas404.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)
DB14/REFBUFEN 1 DIO, DI Data bit 14 input/output
Output is '0' for the ADS8557, ADS8558		 Hardware mode (HW/SW = 0):
Reference buffers enable input.
When low, all reference buffers are enabled (mandatory if internal reference is used). When high, all reference buffers are disabled.
Software mode (HW/SW = 1):
Connect to BGND or BVDD.
The reference buffers are controlled by bit C24 (REFBUF) in control register (CR).
DB13/SDI 2 DIO, DI Data bit 13 input/output
Output is MSB for the ADS8557
and '0' for the ADS8558		 Hardware mode (HW/SW = 0):
Connect to BGND
Software mode (HW/SW = 1):
Serial data input
DB12 3 DIO Data bit 12 input/output
Output is '0' for the ADS8558		 Connect to BGND
DB11 4 DIO Data bit 11 input/output
Output is MSB for the ADS8558		 Connect to BGND
DB10/SDO_C 5 DIO, DO Data bit 10 input/output When SEL_C = 1, data output for channel C
When SEL_C = 0, tie this pin to BGND
DB9/SDO_B 6 DIO, DO Data bit 9 input/output When SEL_B = 1, data output for channel B
When SEL_B = 0, tie this pin to BGND
When SEL_C = 0, data from channel C1 are also available on this output
DB8/SDO_A 7 DIO, DO Data bit 8 input/output Data output for channel A
When SEL_C = 0, data from channel C0 are also available on this output
When SEL_C = 0 and SEL_B = 0, SDO_A acts as the single data output for all channels
BGND 8 P Buffer IO ground, connect to digital ground plane
BVDD 9 P Buffer IO supply, connect to digital supply (2.7 V to 5.5 V). Decouple with a 1-μF ceramic capacitor or a combination of 100-nF and 10-μF ceramic capacitors to BGND.
DB7/HBEN/DCEN 10 DIO, DI, DI Word mode (WORD/BYTE = 0): Data bit 7 input/output Daisy-chain enable input.
When high, DB[5:3] serve as daisy-chain inputs DCIN[A:C]. If daisy-chain mode is not used, connect to BGND.
Byte mode (WORD/BYTE = 1):
High byte enable input.
When high, the high byte is output first on DB[15:8]. When low, the low byte is output first on DB[15:8].
DB6/SCLK 11 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 6 input/output		 Serial interface clock input (36 MHz, max)
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
DB5/DCIN_A 12 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 5 input/output		 When DCEN = 1, daisy-chain data input for channel A.
When DCEN = 0, connect to BGND.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
DB4/DCIN_B 13 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 4 input/output		 When SEL_B = 1 and DCEN = 1,
daisy-chain data input for channel B.
When DCEN = 0, connect to BGND.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
DB3/DCIN_C 14 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 3 input/output		 When SEL_C = 1 and DCEN = 1,
daisy-chain data input for channel C.
When DCEN = 0, connect to BGND.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
DB2/SEL_C 15 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 2 input/output		 Select SDO_C input.
When high, SDO_C is active. When low, SDO_C is disabled.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
DB1/SEL_B 16 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 1 input/output		 Select SDO_B input.
When high, SDO_B is active. When low, SDO_B is disabled.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
DB0/SEL_A 17 DIO, DI Word mode (WORD/BYTE = 0):
Data bit 0 (LSB) input/output		 Select SDO_A input.
When high, SDO_A is active. When low, SDO_A is disabled. Must always be high.
Byte mode (WORD/BYTE = 1):
Connect to BGND or BVDD
BUSY/INT 18 DO When CR bit C21 = 0 (BUSY/INT), converter busy status output. Transitions high when a conversion has been started and remains high during the entire process. Transitions low when the conversion data of all six channels are latched to the output register and remains low thereafter.
In sequential mode (SEQ = 1 in the CR), the BUSY output transitions high when a conversion has been started and goes low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed.
When bit C21 = 1 (BUSY/INT in CR), interrupt output. This bit transitions high after a conversion completes and remains high until the conversion result is read.
The polarity of BUSY/INT output can be changed using bit C20 (BUSY L/H) in the control register.
CS/FS 19 DI, DI Chip select input.
When low, the parallel interface is enabled.
When high, the interface is disabled.		 Frame synchronization.
The falling edge of FS controls the frame transfer.
RD 20 DI Read data input.
When low, the parallel data output is enabled.
When high, the data output is disabled.		 Connect to BGND.
CONVST_C 21 DI Hardware mode (HW/SW = 0): Conversion start of channel pair C.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0]. CONVST_C must remain high during the entire conversion cycle, otherwise both ADCs of channel C are put in partial power-down mode (see the Reset and Power-Down Modes section).
Software mode (HW/SW = 1): Conversion start of channel pair C in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise.
CONVST_B 22 DI Hardware mode (HW/SW = 0): Conversion start of channel pair B.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0]. CONVST_B must remain high during the entire conversion cycle; otherwise, both ADCs of channel B are put into partial power-down mode (see the Reset and Power-Down Modes section).
Software mode (HW/SW = 1): Conversion start of channel pair B in sequential mode (CR bit C23 = 1) only; connect to BGND or BVDD otherwise.
CONVST_A 23 DI Hardware mode (HW/SW = 0): Conversion start of channel pair A.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0]. CONVST_A must remain high during the entire conversion cycle; otherwise, both ADCs of channel A are put into partial power-down mode (see the Reset and Power-Down Modes section).
Software mode (HW/SW = 1): Conversion start of all selected channels except in sequential mode
(CR bit C23 = 1): Conversion start of channel pair A only.
STBY 24 DI Standby mode input. When low, the entire device is powered-down (including the internal clock and reference).
When high, the device operates in normal mode.
AGND 25, 32, 37, 38, 43, 44, 49, 52, 53, 55, 57, 59 P Analog ground, connect to analog ground plane
Pin 25 can have a dedicated ground if the difference between its potential and AGND is always kept within ±300 mV.
AVDD 26, 34, 35, 40, 41, 46, 47, 50, 60 P Analog power supply (4.5 V to 5.5 V). Decouple each pin with a 100-nF ceramic capacitor to AGND. Use an additional 10-μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor. Pin 26 can have a dedicated power supply if the difference between its potential and AVDD is always kept within ±300 mV.
RANGE/XCLK 27 DI, DIO Hardware mode (HW/SW = 0): Input voltage range select input.
When low, the analog input range is ±4 VREF. When high, the analog input range is ±2 VREF.
Software mode (HW/SW = 1): External conversion clock input, if CR bit C11 (CLKSEL) is set high or internal conversion clock output, if CR bit C10 (CLKOUT_EN) is set high. If not used, connect to BVDD or BGND.
RESET 28 DI Reset input, active high. Aborts any ongoing conversions. Resets the internal control register to 0x000003FF. The RESET pulse must be at least 50 ns long.
WORD/BYTE 29 DI Output mode selection input.
When low, data are transferred in word mode using DB[15:0]. When high, data are transferred in byte mode using DB[15:8] with the byte order controlled by HBEN pin while two accesses are required for a complete 16-bit transfer.		 Connect to BGND.
HVSS 30 P Negative supply voltage for the analog inputs (–16.5 V to –5 V).
Decouple with a 100-nF ceramic capacitor to AGND placed next to the device and a 10-μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor.
HVDD 31 P Positive supply voltage for the analog inputs (5 V to 16.5 V). Decouple with a 100-nF ceramic capacitor to AGND placed next to the device and a 10-μF capacitor to AGND close to the device but without compromising the placement of the smaller capacitor.
CH_A0 33 AI Analog input of channel A0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode.
CH_A1 36 AI Analog input of channel A1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C26 (RANGE_A) in software mode.
CH_B0 39 AI Analog input of channel B0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode.
CH_B1 42 AI Analog input of channel B1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C27 (RANGE_B) in software mode.
CH_C0 45 AI Analog input of channel C0. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode.
CH_C1 48 AI Analog input of channel C1. The input voltage range is controlled by RANGE pin in hardware mode or CR bit C28 (RANGE_C) in software mode.
REFIO 51 AIO Reference voltage input/output (0.5 V to 3.025 V).
The internal reference is enabled via REFEN/WR pin in hardware mode or CR bit C25 (REFEN) in software mode. The output value is controlled by the internal DAC (CR bits C[9:0]). Connect a 470-nF ceramic decoupling capacitor between this pin and pin 52.
REFC_A 54 AI Decoupling capacitor for reference of channels A.
Connect a 10-μF ceramic decoupling capacitor between this pin and pin 53.
REFC_B 56 AI Decoupling capacitor for reference of channels B.
Connect a 10-μF ceramic decoupling capacitor between this pin and pin 55.
REFC_C 58 AI Decoupling capacitor for reference of channels C.
Connect a 10-μF ceramic decoupling capacitor between this pin and pin 57.
PAR/SER 61 DI Interface mode selection input.
When low, the parallel interface is selected. When high, the serial interface is enabled.
HW/SW 62 DI Mode selection input.
When low, the hardware mode is selected and part works according to the settings of external pins. When high, the software mode is selected in which the device is configured by writing into the control register.
REFEN/WR 63 DI Hardware mode (HW/SW = 0):
Internal reference enable input.
When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference is applied at REFIO.		 Hardware mode (HW/SW = 0):
Internal reference enable input.
When high, the internal reference is enabled (the reference buffers are to be enabled). When low, the internal reference is disabled and an external reference must be applied at REFIO.
Software mode (HW/SW = 1): Write input.
The parallel data input is enabled, when CS and WR are low. The internal reference is enabled by the CR bit C25 (REFEN).		 Software mode (HW/SW = 1): Connect to BGND or BVDD.
The internal reference is enabled by CR bit C25 (REFEN).
DB15 64 DIO Data bit 15 (MSB) input/output.
Output is '0' for the ADS8557/8.		 Connect to BGND.
(1) AI = analog input; AIO = analog input/output; DI = digital input; DO = digital output; DIO = digital input/output; and P = power supply.
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