ZHCSFU0B December   2016  – March 2021 ADS8661 , ADS8665

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 Power-Down (PD) Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表

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订购信息

7.5.2 Input Command Word and Register Write Operation

Any data write operation to the device is always synchronous to the external clock provided on the SCLK pin.

The device allows either one byte or two bytes (equivalent to half a word) to be read or written during any device programming operation. Table 7-5 lists the input commands supported by the device. The input commands associated with reading or writing two bytes in a single operation are suffixed as HWORD.

For any HWORD command, the LSB of the 9-bit address is always ignored and considered as 0b. For example, regardless whether address 04h or 05h is entered for any particular HWORD command, the device always exercises the command on address 04h.

Table 7-5 List of Input Commands
OPCODE
B[31:0]		 COMMAND ACRONYM COMMAND DESCRIPTION
00000000_000000000_
00000000_00000000		 NOP No operation
11000_xx_<9-bit address>_
<16-bit data>(1)		 CLEAR_HWORD
  • Command used to clear any (or a group of) bits of a register.
  • Any bit marked 1 in the data field results in that particular bit of the specified register being reset to 0, leaving the other bits unchanged.
  • Half-word command (that is, the command functions on 16 bits at a time).
  • LSB of the 9-bit address is always ignored and considered as 0b.(2)
11001_xx_<9-bit address>_
00000000_00000000		 READ_HWORD
  • Command used to perform a 16-bit read operation.
  • Half-word command (that is, the device outputs 16 bits of register data at a time).
  • LSB of the 9-bit address is always ignored and considered as 0b.
  • Upon receiving this command, the device sends out 16 bits of the register in the next frame.
01001_xx_<9-bit address>_
00000000_00000000		 READ
  • Same as the READ_HWORD except that only eight bits of the register (byte read) are returned in the next frame.
11010_00_<9-bit address>_
<16-bit data>		 WRITE
  • Half-word write command (two bytes of input data are written into the specified address).
  • LSB of the 9-bit address is always ignored and considered as 0b.
11010_01_<9-bit address>_
<16-bit data>
  • Half-word write command.
  • LSB of the 9-bit address is always ignored and considered as 0b.
  • With this command, only the MS byte of the 16-bit data word is written at the specified register address. The LS byte is ignored.
11010_10_<9-bit address>_
<16-bit data>
  • Half-word write command.
  • LSB of the 9-bit address is always ignored and considered as 0b.
  • With this command, only the LS byte of the 16-bit data word is written at the specified register address. The MS byte is ignored.
11011_xx_<9-bit address>_
<16-bit data>		 SET_HWORD
  • Command used to set any (or a group of) bits of a register.
  • Any bit marked 1 in the data field results in that particular bit of the specified register being set to 1, leaving the other bits unchanged.
  • Half-word command (that is, the command functions on 16 bits at a time).
  • LSB of the 9-bit address is always ignored and considered as 0b.
All other input command combinations NOP No operation
(1) <9-bit address> is realized by adding a 0 at the MSB location followed by an 8-bit register address as defined in Table 7-10. The <9-bit address> for register 0x04h is 0x0-0000-0100b.
(2) An HWORD command operates on a set of 16 bits in the register map that is usually identified as two registers of eight bits each. For example, the command 11000_xx_<0_0000_0101><16-bit data> is treated the same as the command 11000_xx_<0_0000_0100><16-bit data> for bits 15:0 of the RST_PWRCTL_REG register.

All input commands (including the CLEAR_HWORD, WRITE, and SET_HWORD commands listed in Table 7-5) used to configure the internal registers must be 32 bits long. If any of these commands are provided in a particular data frame F, that command gets executed at the rising edge of the CONVST/CS signal.
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