The device allows the output clock on the RVS pin to be synchronous to either the external clock provided on the SCLK pin or to the internal clock of the device. This selection is done by configuring the SSYNC_CLK bit, as explained in the SDO_CTL_REG register. The timing diagram and specifications for operating the device with an SRC protocol in external CLK mode are provided in Figure 6-7 and the Section 6.9 table. The timing diagram and specifications for operating the device with an SRC protocol in internal CLK mode are provided in Figure 6-8 and the Section 6.10 table.