ADS9110 18 位、2MSPS、15mW SAR ADC，具有 multiSPI 接口
- ZHCSE95A October 2015 – October 2015 ADS9110
  
  PRODUCTION DATA.

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ADS9110 18 位、2MSPS、15mW SAR ADC，具有 multiSPI 接口

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1 特性

采样率：2MSPS
无延迟输出
出色的直流和交流性能：
- 积分非线性 (INL)：±0.5 最低有效位 (LSB)（典型值），±1.5 LSB（最大值）
- 微分非线性 (DNL)：±0.75 LSB（最大值），18 位无丢码 (NMC)
- 信噪比 (SNR)：100dB
- 总谐波失真 (THD)：-118dB
宽输入范围：
- 单极差分输入范围：±V_REF
- V_REF 输入范围：2.5V 至 5V，
  与 AVDD 无关
低功耗：
- 2MSPS 时为 9mW（仅限 AVDD）
- 2MSPS 时为 15mW（总功耗）
- 灵活的低功耗模式，可根据吞吐量调节功率
multiSPI：增强型串行接口
符合 JESD8-7A 标准的数字 I/O（1.8V DVDD 时）
在 -40°C 至 +85°C 的工业温度范围内完全额定运行
小型封装：4mm × 4mm 超薄四方扁平无引线 (VQFN) 封装

2 应用

测试和测量
医疗成像
高精度、高速工业领域

3 说明

ADS9110 是一款 18 位、2MSPS、逐次逼近寄存器 (SAR) 模数转换器 (ADC)，在典型工作条件下具有 ±0.5 LSB INL 和 100dB SNR 规范值。高吞吐量使得开发者能够对输入信号进行过采样，从而提高测量的动态范围和精度。

该器件支持单极全差分模拟输入信号，并采用 2.5V 至 5V 的外部基准电压，能够提供宽输入选择范围，无需额外进行输入调节。

该器件以 2MSPS 全吞吐量运行时的功耗仅为 15mW。吞吐量较低时，可灵活使用低功耗模式（NAP 和 PD）来降低功耗。

集成的 multiSPI 串行接口向后兼容传统 SPI™ 协议。此外，该器件的可配置功能还能够简化电路板布局、时序和固件，并且以低时钟速度运行时能够获得高吞吐量，因此可轻松连接各种微控制器、数字信号处理器 (DSP) 以及现场可编程门阵列 (FPGA)。

该器件采用节省空间的 4mm × 4mm VQFN 封装，支持符合 JESD8-7A 标准的 I/O 和标准工业温度范围。

器件信息

部件号	封装	封装尺寸（标称值）
ADS9110	VQFN (24)	4.00mm x 4.00mm

如需了解所有可用封装，请见数据表末尾的可订购米6体育平台手机版_好二三四附录。

典型应用图以及积分非线性度与代码间的关系图

4 修订历史记录

Changes from * Revision (October 2015) to A Revision

已发布为量产数据Go

5 Pin Configuration and Functions

RGE Package

VQFN-24

Top View

Pin Functions

PIN		FUNCTION	DESCRIPTION
NAME	NO.	FUNCTION	DESCRIPTION
AINM	10	Analog input	Negative analog input
AINP	9	Analog input	Positive analog input
AVDD	13, 14	Power supply	Analog power supply for the device
CONVST	1	Digital input	Conversion start input pin for the device. A CONVST rising edge brings the device from ACQ state to CNV state.
CS	24	Digital input	Chip-select input pin for the device; active low The device takes control of the data bus when CS is low. The SDO-x pins go to tri-state when CS is high.
DVDD	16	Power supply	Interface supply
GND	11, 15	Power supply	Ground
NC	3, 6, 12	No connection	These pins must be left floating with no external connection
REFM	4, 8	Analog input	Reference ground potential
REFP	5, 7	Analog input	Reference voltage input
RST	2	Digital input	Asynchronous reset input pin for the device. A low pulse on the RST pin resets the device and all register bits return to their default state.
RVS	21	Digital output	Multi-function output pin for the device. With CS held high, RVS reflects the status of the internal ADCST signal. With CS low, the status of RVS depends on the output protocol selection.
SCLK	23	Digital input	Clock input pin for the serial interface. All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SDI	22	Digital input	Serial data input pin for the device. This pin is used to feed the data or command into the device.
SDO-0	20	Digital output	Serial communication: data output 0
SDO-1	19	Digital output	Serial communication: data output 1
SDO-2	18	Digital output	Serial communication: data output 2
SDO-3	17	Digital output	Serial communication: data output 3
Thermal pad		Supply	Exposed thermal pad; connecting this pin to GND is recommended

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
AVDD to GND	–0.3	2.1	V
DVDD to GND	–0.3	2.1	V
REFP to REFM	–0.3	5.5	V
REFM to GND	–0.1	0.1	V
Analog (AINP, AINM) to GND	–0.3	REFP + 0.3	V
Digital input (RST, CONVST, CS, SCLK, SDI) to GND	–0.3	DVDD + 0.3	V
Digital output (RVS, SDO-0, SDO-1, SDO-2, SDO-3) to GND	–0.3	DVDD + 0.3	V
Operating temperature, T_A	–40	85	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		NOM	UNIT
AVDD	Analog supply voltage	1.8	V
DVDD	Digital supply voltage	1.8	V
REFP	Positive reference	5	V

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS9110	UNITS
		RGE (VQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	31.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	29.9	°C/W
R_θJB	Junction-to-board thermal resistance	8.9	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	8.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.0	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, V_REF = 5 V, and f_DATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for T_A = –40°C to +85°C. All typical values are at T_A = 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUT
FSR	Full-scale input range (AINP – AINM)⁽¹⁾		–V_REF		V_REF	V
V_IN	Absolute input voltage (AINP and AINM to REFGND)		–0.1		V_REF + 0.1	V
V_CM	Common-mode voltage range (AINP + AINM) / 2		(V_REF / 2) – 0.1	V_REF / 2	(V_REF / 2) + 0.1	V
C_IN	Input capacitance	In sample mode		60		pF
C_IN	Input capacitance	In hold mode		4		pF
I_IL	Input leakage current			±1		µA
VOLTAGE REFERENCE INPUT
V_REF	Reference input voltage range		2.5		5	V
I_REF	Reference input current	Average current, V_REF = 5 V, 2-kHz, full-scale input, throughput = 2 MSPS		1.25		mA
DC ACCURACY
	Resolution			18		Bits
NMC	No missing codes		18			Bits
INL	Integral nonlinearity	In LSBs	–1.5	±0.5⁽²⁾	1.5	LSB⁽³⁾
INL	Integral nonlinearity	In ppm	–5.7	±2	5.7	ppm
DNL	Differential nonlinearity		–0.75	±0.4⁽²⁾	0.75	LSB⁽³⁾
E_(IO)	Input offset error		–1	±0.05⁽²⁾	1	mV
dV_OS/dT	Input offset thermal drift			1		μV/°C
G_E	Gain error		–0.01	±0.005⁽²⁾	0.01	%FS
G_E/dT	Gain error thermal drift			0.25		ppm/°C
	Transition noise			0.9		LSB⁽³⁾
CMRR	Common-mode rejection ratio	At dc to 20 kHz		80		dB
AC ACCURACY⁽⁴⁾
SINAD	Signal-to-noise + distortion	f_IN = 2 kHz	98	99.9		dB
		f_IN = 100 kHz		95.4
		f_IN = 500 kHz		89
SNR	Signal-to-noise ratio	f_IN = 2 kHz	98.1	100		dB
		f_IN = 100 kHz		95.5
		f_IN = 500 kHz		89.3
THD	Total harmonic distortion⁽⁵⁾	f_IN = 2 kHz		–118		dB
		f_IN = 100 kHz		–111
		f_IN = 500 kHz		–101
SFDR	Spurious-free dynamic range	f_IN = 2 kHz		123		dB
		f_IN = 100 kHz		116
		f_IN = 500 kHz		106
DIGITAL INPUTS⁽⁶⁾
V_IH	High-level input voltage		0.65 DVDD		DVDD + 0.3	V
V_IL	Low-level input voltage		–0.3		0.35 DVDD	V
DIGITAL OUTPUTS⁽⁶⁾
V_OH	High-level output voltage	I_OH = 2-mA source	DVDD – 0.45			V
V_OL	Low-level output voltage	I_OH = 2-mA sink			0.45	V
POWER SUPPLY
AVDD	Analog supply voltage		1.65	1.8	1.95	V
DVDD	Digital supply voltage		1.65	1.8	1.95	V
IDD	AVDD supply current (AVDD = 1.8 V)	Active, fastest throughput		5	6.25	mA
		Static, ACQ state		3.7		mA
		Low-power, NAP mode		500		µA
		Power-down, PD state		1		µA
P_D	AVDD power dissipation (AVDD = 1.8 V)	Active, fastest throughput		9	11.25	mW
		Static, ACQ state		6.6		mW
		Low-power, NAP mode		900		µW
		Power-down, PD state		1.8		µW
TEMPERATURE RANGE
T_A	Operating free-air temperature		–40		85	°C

(1) Ideal input span, does not include gain or offset errors.

(2) See Figure 9, Figure 10, Figure 25, and Figure 26 for statistical distribution data for INL, DNL, offset, and gain error parameters.

(3) LSB = least-significant bit. 1 LSB at 18 bits is approximately 3.8 ppm.

(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.1 dB below full-scale, unless otherwise specified.

(5) Calculated on the first nine harmonics of the input frequency.

(6) As per the JESD8-7A standard. Specified by design; not production tested.

6.6 Timing Requirements: Conversion Cycle

		MIN	MAX	UNIT
TIMING REQUIREMENTS
f_cycle	Sampling frequency		2	MHz
t_cycle	ADC cycle time period	500		ns
t_{wh_CONVST}	Pulse duration: CONVST high	30		ns
t_{wl_CONVST}	Pulse duration: CONVST low	30		ns
t_acq	Acquisition time	150		ns
t_{qt_acq}	Quiet acquisition time⁽¹⁾	25		ns
t_{d_cnvcap}	Quiet aperture time⁽¹⁾	10		ns
TIMING SPECIFICATIONS
t_conv	Conversion time	300	340	ns

(1) See Figure 48.

6.7 Timing Requirements: Asynchronous Reset, NAP, and PD

		MIN	MAX	UNIT
TIMING REQUIREMENTS
t_{wl_RST}	Pulse duration: RST low	100		ns
TIMING SPECIFICATIONS
t_{d_rst}	Delay time: RST rising to RVS rising		1250	µs
t_{nap_wkup}	Wake-up time: NAP mode		300	ns
t_PWRUP	Power-up time: PD mode		250	µs

6.8 Timing Requirements: SPI-Compatible Serial Interface

			MIN	MAX	UNIT
TIMING REQUIREMENTS
f_CLK	Serial clock frequency			75	MHz
t_CLK	Serial clock time period		13.33		ns
t_{ph_CK}	SCLK high time		0.45	0.55	t_CLK
t_{pl_CK}	SCLK low time		0.45	0.55	t_CLK
t_{su_CSCK}	Setup time: CS falling to the first SCLK capture edge		5		ns
t_{su_CKDI}	Setup time: SDI data valid to the SCLK capture edge		1.2		ns
t_{ht_CKDI}	Hold time: SCLK capture edge to (previous) data valid on SDI		0.65		ns
t_{ht_CKCS}	Delay time: last SCLK falling to CS rising		5		ns
TIMING SPECIFICATIONS
t_{den_CSDO}	Delay time: CS falling to data enable			4.5	ns
t_{dz_CSDO}	Delay time: CS rising to SDO going to 3-state			10	ns
t_{d_CKDO}	Delay time: SCLK launch edge to (next) data valid on SDO			6.5	ns
t_{d_CSRDY_f}	Delay time: CS falling to RVS falling			5	ns
t_{d_CSRDY_r}	Delay time: CS rising to RVS rising	After NOP operation		10	ns
t_{d_CSRDY_r}	Delay time: CS rising to RVS rising	After WR or RD operation		70	ns

6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)

		MIN	MAX	UNIT
TIMING REQUIREMENTS
f_CLK	Serial clock frequency		100	MHz
t_CLK	Serial clock time period	10		ns
TIMING SPECIFICATIONS⁽¹⁾
t_{d_CKSTR_r}	Delay time: SCLK launch edge to RVS rising		8.5	ns
t_{d_CKSTR_f}	Delay time: SCLK launch edge to RVS falling		8.5	ns
t_{off_STRDO_f}	Time offset: RVS rising to (next) data valid on SDO	–0.5	0.5	ns
t_{off_STRDO_r}	Time offset: RVS falling to (next) data valid on SDO	–0.5	0.5	ns

(1) Other parameters are the same as the Timing Requirements: SPI-Compatible Serial Interface table.

6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)

			MIN	MAX	UNIT
TIMING SPECIFICATIONS⁽¹⁾
t_{d_CSSTR}	Delay time: CS falling to RVS rising		12	40	ns
t_{off_STRDO_f}	Time offset: RVS rising to (next) data valid on SDO		–0.5	0.5	ns
t_{off_STRDO_r}	Time offset: RVS falling to (next) data valid on SDO		–0.5	0.5	ns
t_STR	Strobe output time period	INTCLK option	9.9	11.1	ns
		INTCLK / 2 option	19.8	22.2
		INTCLK / 4 option	39.6	44.4
t_{ph_STR}	Strobe output high time		0.45	0.55	t_STR
t_{pl_STR}	Strobe output low time		0.45	0.55	t_STR

Figure 1. Conversion Cycle Timing Diagram

Figure 2. Asynchronous Reset Timing Diagram

Figure 3. NAP Mode Timing Diagram

1. The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.

Figure 4. SPI-Compatible Serial Interface Timing Diagram

Figure 5. Source-Synchronous Serial Interface Timing Diagram (External Clock)

Figure 6. Source-Synchronous Serial Interface Timing Diagram (Internal Clock)

6.11 Typical Characteristics

At T_A = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, V_REF = 5 V, and f_SAMPLE = 2 MSPS, unless otherwise noted.

Typical INL = ±0.5 LSB

Figure 7. Typical INL

600 devices

Figure 9. Typical INL Distribution

V_REF = 5 V

Figure 11. INL vs Temperature

T_A = 25°C

Figure 13. INL vs Reference Voltage

Standard deviation = 0.9 LSB

Figure 15. DC Input Histogram, Code Ceter

f_IN = 2 kHz, SNR = 100 dB, THD = –120 dB

Figure 17. Typical FFT

f_IN = 2 kHz, V_REF = 5 V

Figure 19. Noise Performance vs Temperature

f_IN = 2 kHz, T_A = 25°C

Figure 21. Noise Performance vs Reference Voltage

V_REF = 5 V, T_A = 25°C

Figure 23. Noise Performance vs Input Frequency

600 devices

Figure 25. Offset Typical Distribution

V_REF = 5 V

Figure 27. Offset vs Temperature

T_A = 25°C

Figure 29. Offset vs Reference Voltage

2 MSPS

Figure 31. Supply Current vs Temperature

2 MSPS

Figure 33. Reference Current vs Temperature

Figure 35. CMRR vs Input Frequency

Typical DNL = ±0.4 LSB

Figure 8. Typical DNL

600 devices

Figure 10. Typical DNL Distribution

V_REF = 5 V

Figure 12. DNL vs Temperature

T_A = 25°C

Figure 14. DNL vs Reference Voltage

Standard deviation = 0.9 LSB

Figure 16. DC Input Histogram, Code Transition

f_IN = 100 kHz, SNR = 97.5 dB, THD = –113 dB

Figure 18. Typical FFT

f_IN = 2 kHz, V_REF = 5 V

Figure 20. Distortion Performance vs Temperature

f_IN = 2 kHz, T_A = 25°C

Figure 22. Distortion Performance vs Reference Voltage

V_REF = 5 V, T_A = 25°C

Figure 24. Distortion Performance vs Input Frequency

600 devices

Figure 26. Gain Error Typical Distribution

V_REF = 5 V

Figure 28. Gain Error vs Temperature

T_A = 25°C

Figure 30. Gain Error vs Reference Voltage

T_A = 25°C

Figure 32. Supply Current vs Throughput

T_A = 25°C

Figure 34. Reference Current vs Throughput