7.3.1 Converter Module

As shown in Figure 37, the converter module samples the analog input signal (provided between the AINP and AINM pins), compares this signal with the reference voltage (provided between the pair of REFP and REFM pins), and generates an equivalent digital output code.

The converter module receives RST and CONVST inputs from the interface module and outputs the ADCST signal and the conversion result back to the interface module.

7.3.2 Interface Module

The interface module facilitates the communication and data transfer between the device and the host controller. As shown in Figure 41, the module comprises of shift registers (both input and output), configuration registers, and a protocol unit.

The Pin Configuration and Functions section provides descriptions of the interface pins; the Data Transfer Frame section details the functions of shift registers, the SCLK counter, and the command processor; the Data Transfer Protocols section details supported protocols; and the Register Maps section explains the configuration registers and bit settings.

7.4.1 RST State

In the ADS9110, the RST pin is an asynchronous digital input. To enter RST state, the host controller must pull the RST pin low and keep it low for the t_{wl_RST} duration (as specified in the Timing Requirements: Asynchronous Reset, NAP, and PD table).

In RST state, all configuration registers (see the Register Maps section) are reset to their default values, the RVS pins remain low, and the SDO-x pins are tri-stated.

To exit RST state, the host controller must pull the RST pin high with CONVST and SCLK held low and CS held high, as shown in Figure 43. After a delay of t_{d_rst}, the device enters ACQ state and the RVS pin goes high.

7.4.2 ACQ State

In ACQ state, the device acquires the analog input signal. The device enters ACQ state on power-up, after any asynchronous reset, or after end of every conversion.

An RST falling edge takes the device from an ACQ state to a RST state. A CONVST rising edge takes the device from an ACQ state to a CNV state.

The device offers a low-power NAP mode to reduce power consumption in the ACQ state; see the NAP Mode section for more details on NAP mode.

7.4.3 CNV State

The device moves from ACQ state to CNV state on a rising edge of the CONVST pin. The conversion process uses an internal clock and the device ignores any further transitions on the CONVST signal until the ongoing conversion is complete (that is, during the time interval of t_conv).

At the end of conversion, the device enters ACQ state. The cycle time for the device is given by Equation 4:

NOTE

The conversion time, t_conv, can vary within the specified limits of t_{conv_min} and t_{conv_max} (as specified in the Timing Requirements: Conversion Cycle table). After initiating a conversion, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the t_{conv_max} duration to elapse before initiating a new operation (data transfer or conversion). If RVS is not monitored, substitute t_conv in Equation 4 with t_{conv_max}.

Table 2. Supported Commands

OPCODE B[19:0]	COMMAND ACRONYM	COMMAND DESCRIPTION
0000_0000_0000_0000_0000	NOP	No operation
1001_<8-bit address>_0000_0000	RD_REG	Read contents from the <8-bit address>
1010_<8-bit address>_<8-bit data>	WR_REG	Write <8-bit data> to the <8-bit address>
1111_1111_1111_1111_1111	NOP	No operation
Remaining combinations	Reserved	These commands are reserved and treated by the device as no operation

7.5.1 Data Transfer Frame

A data transfer frame between the device and the host controller is bounded between a CS falling edge and the subsequent CS rising edge. The host controller can initiate a data transfer frame (as shown in Figure 47) at any time irrespective of the status of the CONVST signal; however, the data read during such a data transfer frame is a function of relative timing between the CONVST and CS signals.

For this discussion, assume that the CONVST signal remains low.

For a typical data transfer frame F:

1. The host controller pulls CS low to initiate a data transfer frame. On the CS falling edge:
   • RVS goes low, indicating the beginning of the data transfer frame.
   • The SCLK counter is reset to 0.
   • The device takes control of the data bus. As shown in Figure 47, the 20-bit contents of the output data word (see Figure 45) are loaded in to the 20-bit OSR (see Figure 41).
   • The 20-bit ISR (see Figure 41) is reset to 00000h, corresponding to a NOP command.
2. During the frame, the host controller provides clocks on the SCLK pin:
   • On each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted in to the ISR.
   • On each launch edge of the output clock (SCLK in this case), OSR data are shifted out on the selected SDO-x pins.
   • The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From the Device section).
3. The host controller pulls CS high to end the data transfer frame. On the CS rising edge:
   • The SDO-x pins go to tri-state.
   • RVS goes high (after a delay of t_{d_RVS}).
   • As illustrated in Figure 47, the 20-bit contents of the ISR are transferred to the command processor (see Figure 41) for decoding and further action.

After pulling CS high, the host controller must monitor for a low-to-high transition on the RVS pin or wait for the t_{d_RVS} time (see the Timing Requirements: SPI-Compatible Serial Interface table) to elapse before initiating a new operation (data transfer or conversion). The delay, t_{d_RVS}, for any data transfer frame F varies based on the data transfer operation executed in the frame F.

At the end of the data transfer frame F:

• If the SCLK counter is < 20, then the device treats the frame F as a short data transfer frame. The output data bits transferred during such a short data transfer frame are still valid data; however, the device ignores the data received over the SDI pin (similar to a no operation command). The host controller can use these short data transfer frames to read only the required number of MSB bits from the 20-bit output data word.
• If the SCLK counter = 20, then the device treats the frame F as a optimal data transfer frame. At the end of an optimal data transfer frame, the command processor treats the 20-bit contents of the ISR as a valid command word.
• If the SCLK counter > 20, then the device treats the frame F as a long data transfer frame. At the end of a long data transfer frame, the command processor treats the 20-bit contents of the ISR as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, when the host controller provides a long data transfer frame, the last 20 bits shifted into the device prior to the CS rising edge must constitute the desired command.

NOTE

This example shows a data transfer synchronous to the external clock provided on the SCLK pin. The device also supports data transfer operations that are synchronous to the internal clock; see the Protocols for Reading From the Device section for more details.

7.5.2 Interleaving Conversion Cycles and Data Transfer Frames

The host controller can operate the ADS9110 at the desired throughput by interleaving the conversion cycles and the data transfer frames.

The cycle time of the device, t_cycle, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, t_resp, is the time difference between the host controller initiating a conversion C and the host controller receiving the complete result for conversion C.

Figure 48 shows three conversion cycles, C, C+1, and C+2. Conversion C is initiated by a CONVST rising edge at the t = 0 time and the conversion result becomes available for data transfer at the t_conv time. However, this result is loaded into the OSR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of the conversion C+1 (that is, before the t_cycle + t_conv time).

To achieve the rated performance specifications, the host controller must ensure that no digital signals toggle during the quiet acquisition time (t_{qt_acq}) and quiet aperture time (t_{d_cnvcap}). Any noise during t_{d_cnvcap} can negatively affect the result of the ongoing conversion whereas any noise during t_{qt_acq} can negatively affect the result of the subsequent conversion.

This architecture allows for two distinct time zones (zone1 and zone2) to transfer data for each conversion. Zone1 and zone2 for conversion C are defined in Table 3.

The response time includes the conversion time and the data transfer time, and is thus a function of the data transfer zone selected.

Figure 49 and Figure 50 illustrate interleaving of three conversion cycles (C, C+1, and C+2) with three data transfer frames (F, F+1, and F+2) in zone1 and in zone2, respectively.

To achieve cycle time, t_cycle, the read time in zone1 is given by Equation 5:

For an optimal data transfer frame, Equation 5 results in an SCLK frequency given by Equation 6:

Then, the zone1 data transfer achieves a response time defined by Equation 7:

As an example, while operating the ADS9110 at its full throughput of 2 MSPS, the host controller can achieve a response time of 1 µs provided that the data transfer in zone1 is completed within 135 ns. However, to achieve this response time, the SCLK frequency must be greater than 148 MHz.

Note that the device does not support such high SCLK speeds. At lower SCLK speeds, t_read-Z1 increases, resulting in slower response times and higher cycle times.

To achieve the same cycle time, t_cycle, the read time in zone2 is given by Equation 8:

For an optimal data transfer frame, Equation 8 results in an SCLK frequency given by Equation 9:

Then, the zone2 data transfer achieves a response time defined by Equation 10:

As an example, the host controller can operate the ADS9110 at its full throughput of 2 MSPS using zone2 data transfer with a 43 MHz SCLK (and a read time of 465 ns). However, zone2 data transfer will result in response time of nearly 2 µs.

Any increase in t_read-Z2 increases response time and can increase cycle time.

For a given cycle time, the zone1 data transfer clearly achieves faster response time but also requires a higher SCLK speed (as evident from Equation 5, Equation 6, and Equation 7), whereas the zone2 data transfer clearly requires a lower SCLK speed but supports slower response time (as evident from Equation 8, Equation 9, and Equation 10).

NOTE

In zone2, the data transfer is active when the device is converting for the next analog sample. This digital activity can interfere with the ongoing conversion and cause some degradation in SNR performance.

Additionally, a data transfer frame can begin in zone1 and then extend into zone2; however, the host controller must ensure that no digital transitions occur during the t_{qt_acq} and t_{d_cnvcap} time intervals.

7.5.3 Data Transfer Protocols

The device features a multiSPI interface that allows the host controller to operate at slower SCLK speeds and still achieve the required cycle time with a faster response time. The multiSPI interface module offers two options to reduce the SCLK speed required for data transfer:

1. An option to increase the width of the output data bus
2. An option to enable double data rate (DDR) transfer

These two options can be combined to achieve further reduction in SCLK speed.

Figure 51 shows the delays between the host controller and the device in a typical serial communication.

The total delay in the path is given by Equation 11:

In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK edges. Therefore, the t_{d_total_serial} delay must be kept less than half of the SCLK duration. Equation 12 shows the fastest clock allowed by the SPI protocol.

Larger values of the t_{d_total_serial} delay restrict the maximum SCLK speed for the SPI protocol, resulting in higher read and response times, and can increase cycle times. To remove this restriction on the SCLK speed, the multiSPI interface module supports an ADC-master or source-synchronous mode of operation.

As illustrated in Figure 52, in ADC-master or source-synchronous mode, the device provides a synchronous output clock (on the RVS pin) along with the output data (on the SDO-x pins).

For a source-synchronous data transfer, the total delay in the path is given by Equation 13:

As illustrated in Equation 11 and Equation 13, the ADC-master or source-synchronous mode completely eliminates the affect of isolator delays and the clock-to-data delays, which are typically the largest contributors in the overall delay computation.

Furthermore, the actual values of t_{pcb_RVS} and t_{pcb_SDO} do not matter. In most cases, the t_{d_total_srcsync} delay can be kept at a minimum by routing the RVS and SDO lines together on the PCB. Therefore, the ADC-master or source-synchronous mode allows the host controller and device to operate at much higher SCLK speeds.

7.5.4 Device Setup

The multiSPI interface and the device configuration registers offer multiple operation modes. This section describes how to select the hardware connection topology to meet different system requirements.

7.6.1 Device Configuration and Register Maps

The device features four configuration registers, mapped as described in Table 8.