ZHCSE95A October   2015  – October 2015 ADS9110

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset, NAP, and PD
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Module
        1. 7.3.1.1 Sample-and-Hold Circuit
        2. 7.3.1.2 External Reference Source
        3. 7.3.1.3 Internal Oscillator
        4. 7.3.1.4 ADC Transfer Function
      2. 7.3.2 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Interleaving Conversion Cycles and Data Transfer Frames
      3. 7.5.3 Data Transfer Protocols
        1. 7.5.3.1 Protocols for Configuring the Device
        2. 7.5.3.2 Protocols for Reading From the Device
          1. 7.5.3.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.3.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.3.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.3.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.3.2.3.2 Bus Width Options with SRC Protocols
            3. 7.5.3.2.3.3 Output Data Rate Options with SRC Protocols
      4. 7.5.4 Device Setup
        1. 7.5.4.1 Single Device: All multiSPI Options
        2. 7.5.4.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.4.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.4.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 010h)
        2. 7.6.1.2 SDI_CNTL Register (address = 014h)
        3. 7.6.1.3 SDO_CNTL Register (address = 018h)
        4. 7.6.1.4 DATA_CNTL Register (address = 01Ch)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
      2. 8.1.2 Input Amplifier Selection
      3. 8.1.3 Antialiasing Filter
      4. 8.1.4 ADC Reference Driver
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power-Supply Recommendations
    1. 9.1 Power-Supply Decoupling
    2. 9.2 Power Saving
      1. 9.2.1 NAP Mode
      2. 9.2.2 PD Mode
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档　
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AVDD to GND –0.3 2.1 V
DVDD to GND –0.3 2.1 V
REFP to REFM –0.3 5.5 V
REFM to GND –0.1 0.1 V
Analog (AINP, AINM) to GND –0.3 REFP + 0.3 V
Digital input (RST, CONVST, CS, SCLK, SDI) to GND –0.3 DVDD + 0.3 V
Digital output (RVS, SDO-0, SDO-1, SDO-2, SDO-3) to GND –0.3 DVDD + 0.3 V
Operating temperature, TA –40 85 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage 1.8 V
DVDD Digital supply voltage 1.8 V
REFP Positive reference 5 V

6.4 Thermal Information

THERMAL METRIC(1) ADS9110 UNITS
RGE (VQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 31.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.9 °C/W
RθJB Junction-to-board thermal resistance 8.9 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 8.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.0 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR Full-scale input range
(AINP – AINM)(1)		 –VREF VREF V
VIN Absolute input voltage
(AINP and AINM to REFGND)		 –0.1 VREF + 0.1 V
VCM Common-mode voltage range
(AINP + AINM) / 2		 (VREF / 2) – 0.1 VREF / 2 (VREF / 2) + 0.1 V
CIN Input capacitance In sample mode 60 pF
In hold mode 4
IIL Input leakage current ±1 µA
VOLTAGE REFERENCE INPUT
VREF Reference input voltage range 2.5 5 V
IREF Reference input current Average current, VREF = 5 V,
2-kHz, full-scale input,
throughput = 2 MSPS		 1.25 mA
DC ACCURACY
Resolution 18 Bits
NMC No missing codes 18 Bits
INL Integral nonlinearity In LSBs –1.5 ±0.5(2) 1.5 LSB(3)
In ppm –5.7 ±2 5.7 ppm
DNL Differential nonlinearity –0.75 ±0.4(2) 0.75 LSB(3)
E(IO) Input offset error –1 ±0.05(2) 1 mV
dVOS/dT Input offset thermal drift 1 μV/°C
GE Gain error –0.01 ±0.005(2) 0.01 %FS
GE/dT Gain error thermal drift 0.25 ppm/°C
Transition noise 0.9 LSB(3)
CMRR Common-mode rejection ratio At dc to 20 kHz 80 dB
AC ACCURACY(4)
SINAD Signal-to-noise + distortion fIN = 2 kHz 98 99.9 dB
fIN = 100 kHz 95.4
fIN = 500 kHz 89
SNR Signal-to-noise ratio fIN = 2 kHz 98.1 100 dB
fIN = 100 kHz 95.5
fIN = 500 kHz 89.3
THD Total harmonic distortion(5) fIN = 2 kHz –118 dB
fIN = 100 kHz –111
fIN = 500 kHz –101
SFDR Spurious-free dynamic range fIN = 2 kHz 123 dB
fIN = 100 kHz 116
fIN = 500 kHz 106
DIGITAL INPUTS(6)
VIH High-level input voltage 0.65 DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.35 DVDD V
DIGITAL OUTPUTS(6)
VOH High-level output voltage IOH = 2-mA source DVDD – 0.45 V
VOL Low-level output voltage IOH = 2-mA sink 0.45 V
POWER SUPPLY
AVDD Analog supply voltage 1.65 1.8 1.95 V
DVDD Digital supply voltage 1.65 1.8 1.95 V
IDD AVDD supply current
(AVDD = 1.8 V)		 Active, fastest throughput 5 6.25 mA
Static, ACQ state 3.7
Low-power, NAP mode 500 µA
Power-down, PD state 1
PD AVDD power dissipation
(AVDD = 1.8 V)		 Active, fastest throughput 9 11.25 mW
Static, ACQ state 6.6
Low-power, NAP mode 900 µW
Power-down, PD state 1.8
TEMPERATURE RANGE
TA Operating free-air temperature –40 85 °C
(1) Ideal input span, does not include gain or offset errors.
(2) See Figure 9, Figure 10, Figure 25, and Figure 26 for statistical distribution data for INL, DNL, offset, and gain error parameters.
(3) LSB = least-significant bit. 1 LSB at 18 bits is approximately 3.8 ppm.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.1 dB below full-scale, unless otherwise specified.
(5) Calculated on the first nine harmonics of the input frequency.
(6) As per the JESD8-7A standard. Specified by design; not production tested.

6.6 Timing Requirements: Conversion Cycle

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 1.
MIN TYP MAX UNIT
TIMING REQUIREMENTS
fcycle Sampling frequency 2 MHz
tcycle ADC cycle time period 500 ns
twh_CONVST Pulse duration: CONVST high 30 ns
twl_CONVST Pulse duration: CONVST low 30 ns
tacq Acquisition time 150 ns
tqt_acq Quiet acquisition time(1) 25 ns
td_cnvcap Quiet aperture time(1) 10 ns
TIMING SPECIFICATIONS
tconv Conversion time 300 340 ns
(1) See Figure 48.

6.7 Timing Requirements: Asynchronous Reset, NAP, and PD

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 2 and Figure 3.
MIN TYP MAX UNIT
TIMING REQUIREMENTS
twl_RST Pulse duration: RST low 100 ns
TIMING SPECIFICATIONS
td_rst Delay time: RST rising to RVS rising 1250 µs
tnap_wkup Wake-up time: NAP mode 300 ns
tPWRUP Power-up time: PD mode 250 µs

6.8 Timing Requirements: SPI-Compatible Serial Interface

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 4.
MIN TYP MAX UNIT
TIMING REQUIREMENTS
fCLK Serial clock frequency 75 MHz
tCLK Serial clock time period 13.33 ns
tph_CK SCLK high time 0.45 0.55 tCLK
tpl_CK SCLK low time 0.45 0.55 tCLK
tsu_CSCK Setup time: CS falling to the first SCLK capture edge 5 ns
tsu_CKDI Setup time: SDI data valid to the SCLK capture edge 1.2 ns
tht_CKDI Hold time: SCLK capture edge to (previous) data valid on SDI 0.65 ns
tht_CKCS Delay time: last SCLK falling to CS rising 5 ns
TIMING SPECIFICATIONS
tden_CSDO Delay time: CS falling to data enable 4.5 ns
tdz_CSDO Delay time: CS rising to SDO going to 3-state 10 ns
td_CKDO Delay time: SCLK launch edge to (next) data valid on SDO 6.5 ns
td_CSRDY_f Delay time: CS falling to RVS falling 5 ns
td_CSRDY_r Delay time:
CS rising to RVS rising		 After NOP operation 10 ns
After WR or RD operation 70

6.9 Timing Requirements: Source-Synchronous Serial Interface (External Clock)

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 5.
MIN TYP MAX UNIT
TIMING REQUIREMENTS
fCLK Serial clock frequency 100 MHz
tCLK Serial clock time period 10 ns
TIMING SPECIFICATIONS(1)
td_CKSTR_r Delay time: SCLK launch edge to RVS rising 8.5 ns
td_CKSTR_f Delay time: SCLK launch edge to RVS falling 8.5 ns
toff_STRDO_f Time offset: RVS rising to (next) data valid on SDO –0.5 0.5 ns
toff_STRDO_r Time offset: RVS falling to (next) data valid on SDO –0.5 0.5 ns
(1) Other parameters are the same as the Timing Requirements: SPI-Compatible Serial Interface table.

6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)

All specifications are for AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fDATA = 2 MSPS, unless otherwise noted.
All minimum and maximum specifications are for TA = –40°C to +85°C. All typical values are at TA = 25°C. See Figure 6.
MIN TYP MAX UNIT
TIMING SPECIFICATIONS(1)
td_CSSTR Delay time: CS falling to RVS rising 12 40 ns
toff_STRDO_f Time offset: RVS rising to (next) data valid on SDO –0.5 0.5 ns
toff_STRDO_r Time offset: RVS falling to (next) data valid on SDO –0.5 0.5 ns
tSTR Strobe output time period INTCLK option 9.9 11.1 ns
INTCLK / 2 option 19.8 22.2
INTCLK / 4 option 39.6 44.4
tph_STR Strobe output high time 0.45 0.55 tSTR
tpl_STR Strobe output low time 0.45 0.55 tSTR
ADS9110 ai_typ_conv_sbas629.gif Figure 1. Conversion Cycle Timing Diagram
ADS9110 tim_reset_sbas629.gif Figure 2. Asynchronous Reset Timing Diagram
ADS9110 ai_nap_conv_cycle_sbas629.gif Figure 3. NAP Mode Timing Diagram
ADS9110 tim_spi_sbas629.gif
1. The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
Figure 4. SPI-Compatible Serial Interface Timing Diagram
ADS9110 tim_srcsync-extclk_sbas629.gif Figure 5. Source-Synchronous Serial Interface Timing Diagram (External Clock)
ADS9110 tim_srcsync-intclk_sbas629.gif Figure 6. Source-Synchronous Serial Interface Timing Diagram (Internal Clock)

6.11 Typical Characteristics

At TA = 25°C, AVDD = 1.8 V, DVDD = 1.8 V, VREF = 5 V, and fSAMPLE = 2 MSPS, unless otherwise noted.
ADS9110 C002_SBAS629.png
Typical INL = ±0.5 LSB
Figure 7. Typical INL
ADS9110 C008_SBAS629.png
600 devices
Figure 9. Typical INL Distribution
ADS9110 C004_SBAS629.png
VREF = 5 V
Figure 11. INL vs Temperature
ADS9110 C006_SBAS629.png
TA = 25°C
Figure 13. INL vs Reference Voltage
ADS9110 C009_SBAS629.png
Standard deviation = 0.9 LSB
Figure 15. DC Input Histogram, Code Ceter
ADS9110 C011_SBAS629.png
fIN = 2 kHz, SNR = 100 dB, THD = –120 dB
Figure 17. Typical FFT
ADS9110 C013_SBAS629.png
fIN = 2 kHz, VREF = 5 V
Figure 19. Noise Performance vs Temperature
ADS9110 C015_SBAS629.png
fIN = 2 kHz, TA = 25°C
Figure 21. Noise Performance vs Reference Voltage
ADS9110 C017_SBAS629.png
VREF = 5 V, TA = 25°C
Figure 23. Noise Performance vs Input Frequency
ADS9110 C023_SBAS629.png
600 devices
Figure 25. Offset Typical Distribution
ADS9110 C019_SBAS629.png
VREF = 5 V
Figure 27. Offset vs Temperature
ADS9110 C021_SBAS629.png
TA = 25°C
Figure 29. Offset vs Reference Voltage
ADS9110 C026_SBAS629.png
2 MSPS
Figure 31. Supply Current vs Temperature
ADS9110 C028_SBAS629.png
2 MSPS
Figure 33. Reference Current vs Temperature
ADS9110 C025_SBAS629.png
Figure 35. CMRR vs Input Frequency
ADS9110 C001_SBAS629.png
Typical DNL = ±0.4 LSB
Figure 8. Typical DNL
ADS9110 C007_SBAS629.png
600 devices
Figure 10. Typical DNL Distribution
ADS9110 C003_SBAS629.png
VREF = 5 V
Figure 12. DNL vs Temperature
ADS9110 C005_SBAS629.png
TA = 25°C
Figure 14. DNL vs Reference Voltage
ADS9110 C010_SBAS629.png
Standard deviation = 0.9 LSB
Figure 16. DC Input Histogram, Code Transition
ADS9110 C012_SBAS629.png
fIN = 100 kHz, SNR = 97.5 dB, THD = –113 dB
Figure 18. Typical FFT
ADS9110 C014_SBAS629.png
fIN = 2 kHz, VREF = 5 V
Figure 20. Distortion Performance vs Temperature
ADS9110 C016_SBAS629.png
fIN = 2 kHz, TA = 25°C
Figure 22. Distortion Performance vs Reference Voltage
ADS9110 C018_SBAS629.png
VREF = 5 V, TA = 25°C
Figure 24. Distortion Performance vs Input Frequency
ADS9110 C024_SBAS629.png
600 devices
Figure 26. Gain Error Typical Distribution
ADS9110 C020_SBAS629.png
VREF = 5 V
Figure 28. Gain Error vs Temperature
ADS9110 C022_SBAS629.png
TA = 25°C
Figure 30. Gain Error vs Reference Voltage
ADS9110 C027_SBAS629.png
TA = 25°C
Figure 32. Supply Current vs Throughput
ADS9110 C029_SBAS629.png
TA = 25°C
Figure 34. Reference Current vs Throughput
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