ZHCSCL7C May   2014  – April 2021 AFE4403

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Family Options
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Requirements: Supply Ramp and Power-Down
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Channel
        1. 8.3.1.1 Receiver Front-End
        2. 8.3.1.2 Ambient Cancellation Scheme and Second Stage Gain Block
        3. 8.3.1.3 Receiver Control Signals
        4. 8.3.1.4 Receiver Timing
      2. 8.3.2 Clocking and Timing Signal Generation
      3. 8.3.3 Timer Module
        1. 8.3.3.1 Using the Timer Module
      4. 8.3.4 Receiver Subsystem Power Path
      5. 8.3.5 Transmit Section
        1. 8.3.5.1 Third LED Support
        2. 8.3.5.2 Transmitter Power Path
        3. 8.3.5.3 LED Power Reduction During Periods of Inactivity
        4. 8.3.5.4 LED Configurations
    4. 8.4 Device Functional Modes
      1. 8.4.1 ADC Operation and Averaging Module
        1. 8.4.1.1 Operation Without Averaging
        2. 8.4.1.2 Operation With Averaging
        3. 8.4.1.3 Dynamic Power-Down Mode
      2. 8.4.2 Diagnostics
        1. 8.4.2.1 Photodiode-Side Fault Detection
        2. 8.4.2.2 Transmitter-Side Fault Detection
        3. 8.4.2.3 Diagnostics Module
    5. 8.5 Programming
      1. 8.5.1 Serial Programming Interface
      2. 8.5.2 Reading and Writing Data
        1. 8.5.2.1 Writing Data
        2. 8.5.2.2 Reading Data
        3. 8.5.2.3 Multiple Data Reads and Writes
        4. 8.5.2.4 Register Initialization
        5. 8.5.2.5 AFE SPI Interface Design Considerations
    6. 8.6 Register Maps
      1. 8.6.1 AFE Register Map
      2. 8.6.2 AFE Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Consumption Considerations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 静电放电警告
    3. 12.3 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

8.6.2 AFE Register Description

Figure 8-37 CONTROL0: Control Register 0 (Address = 00h, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
00000000SW_RSTDIAG_ENTIM_
COUNT_
RST		SPI_
READ

This register is write-only. CONTROL0 is used for AFE software and count timer reset, diagnostics enable, and SPI read functions.

Bits 23:4Must be 0
Bit 3SW_RST: Software reset
0 = No action (default after reset)
1 = Software reset applied; resets all internal registers to the default values and self-clears to 0
Bit 2DIAG_EN: Diagnostic enable
0 = No action (default after reset)
1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set.
At the end of the sequence, all fault status are stored in the DIAG: Diagnostics Flag Register. Afterwards, the DIAG_EN register bit self-clears to 0.
Note that the diagnostics enable bit is automatically reset after the diagnostics completes (16 ms). During the diagnostics mode, ADC data are invalid because of the toggling diagnostics switches.
Bit 1TIM_CNT_RST: Timer counter reset
0 = Disables timer counter reset, required for normal timer operation (default after reset)
1 = Timer counters are in reset state
Bit 0SPI READ: SPI read
0 = SPI read is disabled (default after reset)
1 = SPI read is enabled
Figure 8-38 LED2STC: Sample LED2 Start Count Register (Address = 01h, Reset Value = 0000h)
232221201918171615141312
00000000LED2STC[15:0]
11109876543210
LED2STC[15:0]

This register sets the start timing value for the LED2 signal sample.

Bits 23:16Must be 0
Bits 15:0LED2STC[15:0]: Sample LED2 start count
The contents of this register can be used to position the start of the sample LED2 signal with respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The count is specified as the number of
4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-39 LED2ENDC: Sample LED2 End Count Register (Address = 02h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 LED2ENDC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED2ENDC[15:0]

This register sets the end timing value for the LED2 signal sample.

Bits 23:16Must be 0
Bits 15:0LED2ENDC[15:0]: Sample LED2 end count
The contents of this register can be used to position the end of the sample LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-40 LED2LEDSTC: LED2 LED Start Count Register (Address = 03h, Reset Value = 0000h)
232221201918171615141312
00000000LED2LEDSTC[15:0]
11109876543210
LED2LEDSTC[15:0]

This register sets the start timing value for when the LED2 signal turns on.

Bits 23:16Must be 0
Bits 15:0LED2LEDSTC[15:0]: LED2 start count
The contents of this register can be used to position the start of the LED2 with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-41 LED2LEDENDC: LED2 LED End Count Register (Address = 04h, Reset Value = 0000h)
232221201918171615141312
00000000LED2LEDENDC[15:0]
11109876543210
LED2LEDENDC[15:0]

This register sets the end timing value for when the LED2 signal turns off.

Bits 23:16Must be 0
Bits 15:0LED2LEDENDC[15:0]: LED2 end count
The contents of this register can be used to position the end of the LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-42 ALED2STC: Sample Ambient LED2 Start Count Register (Address = 05h, Reset Value = 0000h)
232221201918171615141312
00000000ALED2STC[15:0]
11109876543210
ALED2STC[15:0]

This register sets the start timing value for the ambient LED2 signal sample.

Bits 23:16Must be 0
Bits 15:0ALED2STC[15:0]: Sample ambient LED2 start count
The contents of this register can be used to position the start of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-43 ALED2ENDC: Sample Ambient LED2 End Count Register
(Address = 06h, Reset Value = 0000h)
232221201918171615141312
00000000ALED2ENDC[15:0]
11109876543210
ALED2ENDC[15:0]

This register sets the end timing value for the ambient LED2 signal sample.

Bits 23:16Must be 0
Bits 15:0ALED2ENDC[15:0]: Sample ambient LED2 end count
The contents of this register can be used to position the end of the sample ambient LED2 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-44 LED1STC: Sample LED1 Start Count Register (Address = 07h, Reset Value = 0000h)
232221201918171615141312
00000000LED1STC[15:0]
11109876543210
LED1STC[15:0]

This register sets the start timing value for the LED1 signal sample.

Bits 23:17Must be 0
Bits 16:0LED1STC[15:0]: Sample LED1 start count
The contents of this register can be used to position the start of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of
4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-45 LED1ENDC: Sample LED1 End Count (Address = 08h, Reset Value = 0000h)
232221201918171615141312
00000000LED1ENDC[15:0]
11109876543210
LED1ENDC[15:0]

This register sets the end timing value for the LED1 signal sample.

Bits 23:17Must be 0
Bits 16:0LED1ENDC[15:0]: Sample LED1 end count
The contents of this register can be used to position the end of the sample LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of
4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-46 LED1LEDSTC: LED1 LED Start Count Register (Address = 09h, Reset Value = 0000h)
232221201918171615141312
00000000LED1LEDSTC[15:0]
11109876543210
LED1LEDSTC[15:0]

This register sets the start timing value for when the LED1 signal turns on.

Bits 23:16Must be 0
Bits 15:0LED1LEDSTC[15:0]: LED1 start count
The contents of this register can be used to position the start of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-47 LED1LEDENDC: LED1 LED End Count Register (Address = 0Ah, Reset Value = 0000h)
232221201918171615141312
00000000LED1LEDENDC[15:0]
11109876543210
LED1LEDENDC[15:0]

This register sets the end timing value for when the LED1 signal turns off.

Bits 23:16Must be 0
Bits 15:0LED1LEDENDC[15:0]: LED1 end count
The contents of this register can be used to position the end of the LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-48 ALED1STC: Sample Ambient LED1 Start Count Register (Address = 0Bh, Reset Value = 0000h)
232221201918171615141312
00000000ALED1STC[15:0]
11109876543210
ALED1STC[15:0]

This register sets the start timing value for the ambient LED1 signal sample.

Bits 23:16Must be 0
Bits 15:0ALED1STC[15:0]: Sample ambient LED1 start count
The contents of this register can be used to position the start of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-49 ALED1ENDC: Sample Ambient LED1 End Count Register
(Address = 0Ch, Reset Value = 0000h)
232221201918171615141312
00000000ALED1ENDC[15:0]
11109876543210
ALED1ENDC[15:0]

This register sets the end timing value for the ambient LED1 signal sample.

Bits 23:16Must be 0
Bits 15:0ALED1ENDC[15:0]: Sample ambient LED1 end count
The contents of this register can be used to position the end of the sample ambient LED1 signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-50 LED2CONVST: LED2 Convert Start Count Register (Address = 0Dh, Reset Value = 0000h)
232221201918171615141312
00000000LED2CONVST[15:0]
11109876543210
LED2CONVST[15:0]

This register sets the start timing value for the LED2 conversion.

Bits 23:16Must be 0
Bits 15:0LED2CONVST[15:0]: LED2 convert start count
The contents of this register can be used to position the start of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-51 LED2CONVEND: LED2 Convert End Count Register (Address = 0Eh, Reset Value = 0000h)
232221201918171615141312
00000000LED2CONVEND[15:0]
11109876543210
LED2CONVEND[15:0]

This register sets the end timing value for the LED2 conversion.

Bits 23:16Must be 0
Bits 15:0LED2CONVEND[15:0]: LED2 convert end count
The contents of this register can be used to position the end of the LED2 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-52 ALED2CONVST: LED2 Ambient Convert Start Count Register
(Address = 0Fh, Reset Value = 0000h)
232221201918171615141312
00000000ALED2CONVST[15:0]
11109876543210
ALED2CONVST[15:0]

This register sets the start timing value for the ambient LED2 conversion.

Bits 23:16Must be 0
Bits 15:0ALED2CONVST[15:0]: LED2 ambient convert start count
The contents of this register can be used to position the start of the LED2 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-53 ALED2CONVEND: LED2 Ambient Convert End Count Register
(Address = 10h, Reset Value = 0000h)
232221201918171615141312
00000000ALED2CONVEND[15:0]
11109876543210
ALED2CONVEND[15:0]

This register sets the end timing value for the ambient LED2 conversion.

Bits 23:16Must be 0
Bits 15:0ALED2CONVEND[15:0]: LED2 ambient convert end count
The contents of this register can be used to position the end of the LED2 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-54 LED1CONVST: LED1 Convert Start Count Register (Address = 11h, Reset Value = 0000h)
232221201918171615141312
00000000LED1CONVST[15:0]
11109876543210
LED1CONVST[15:0]

This register sets the start timing value for the LED1 conversion.

Bits 23:16Must be 0
Bits 15:0LED1CONVST[15:0]: LED1 convert start count
The contents of this register can be used to position the start of the LED1 conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-55 LED1CONVEND: LED1 Convert End Count Register (Address = 12h, Reset Value = 0000h)
232221201918171615141312
00000000LED1CONVEND[15:0]
11109876543210
LED1CONVEND[15:0]

This register sets the end timing value for the LED1 conversion.

Bits 23:16Must be 0
Bits 15:0LED1CONVEND[15:0]: LED1 convert end count
The contents of this register can be used to position the end of the LED1 conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-56 ALED1CONVST: LED1 Ambient Convert Start Count Register
(Address = 13h, Reset Value = 0000h)
232221201918171615141312
00000000ALED1CONVST[15:0]
11109876543210
ALED1CONVST[15:0]

This register sets the start timing value for the ambient LED1 conversion.

Bits 23:16Must be 0
Bits 15:0ALED1CONVST[15:0]: LED1 ambient convert start count
The contents of this register can be used to position the start of the LED1 ambient conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-57 ALED1CONVEND: LED1 Ambient Convert End Count Register
(Address = 14h, Reset Value = 0000h)
232221201918171615141312
00000000ALED1CONVEND[15:0]
11109876543210
ALED1CONVEND[15:0]

This register sets the end timing value for the ambient LED1 conversion.

Bits 23:16Must be 0
Bits 15:0ALED1CONVEND[15:0]: LED1 ambient convert end count
The contents of this register can be used to position the end of the LED1 ambient conversion signal with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
Figure 8-58 ADCRSTSTCT0: ADC Reset 0 Start Count Register (Address = 15h, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTSTCT0[15:0]
11109876543210
ADCRSTSTCT0[15:0]

This register sets the start position of the ADC0 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTSTCT0[15:0]: ADC RESET 0 start count
The contents of this register can be used to position the start of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details.
Figure 8-59 ADCRSTENDCT0: ADC Reset 0 End Count Register (Address = 16h, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTENDCT0[15:0]
11109876543210
ADCRSTENDCT0[15:0]

This register sets the end position of the ADC0 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTENDCT0[15:0]: ADC RESET 0 end count
The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details.
Figure 8-60 ADCRSTSTCT1: ADC Reset 1 Start Count Register (Address = 17h, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTSTCT1[15:0]
11109876543210
ADCRSTSTCT1[15:0]

This register sets the start position of the ADC1 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTSTCT1[15:0]: ADC RESET 1 start count
The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 8-61 ADCRSTENDCT1: ADC Reset 1 End Count Register (Address = 18h, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTENDCT1[15:0]
11109876543210
ADCRSTENDCT1[15:0]

This register sets the end position of the ADC1 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTENDCT1[15:0]: ADC RESET 1 end count
The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 8-62 ADCRSTSTCT2: ADC Reset 2 Start Count Register (Address = 19h, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTSTCT2[15:0]
11109876543210
ADCRSTSTCT2[15:0]

This register sets the start position of the ADC2 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTSTCT2[15:0]: ADC RESET 2 start count
The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 8-63 ADCRSTENDCT2: ADC Reset 2 End Count Register (Address = 1Ah, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTENDCT2[15:0]
11109876543210
ADCRSTENDCT2[15:0]

This register sets the end position of the ADC2 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTENDCT2[15:0]: ADC RESET 2 end count
The contents of this register can be used to position the end of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 8-64 ADCRSTSTCT3: ADC Reset 3 Start Count Register (Address = 1Bh, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTSTCT3[15:0]
11109876543210
ADCRSTSTCT3[15:0]

This register sets the start position of the ADC3 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTSTCT3[15:0]: ADC RESET 3 start count
The contents of this register can be used to position the start of the ADC reset conversion. Refer to the Using the Timer Module section for details.
Figure 8-65 ADCRSTENDCT3: ADC Reset 3 End Count Register (Address = 1Ch, Reset Value = 0000h)
232221201918171615141312
00000000ADCRSTENDCT3[15:0]
11109876543210
ADCRSTENDCT3[15:0]

This register sets the end position of the ADC3 reset conversion signal.

Bits 23:16Must be 0
Bits 15:0ADCRSTENDCT3[15:0]: ADC RESET 3 end count
The contents of this register can be used to position the end of the ADC reset conversion signal (default value after reset is 0000h). Refer to the Using the Timer Module section for details.
Figure 8-66 PRPCOUNT: Pulse Repetition Period Count Register (Address = 1Dh, Reset Value = 0000h)
232221201918171615141312
00000000PRPCOUNT[15:0]
11109876543210
PRPCOUNT[15:0]

This register sets the device pulse repetition period count.

Bits 23:16Must be 0
Bits 15:0PRPCOUNT[15:0]: Pulse repetition period count
The contents of this register can be used to set the pulse repetition period (in number of clock cycles of the 4-MHz clock). The PRPCOUNT value must be set in the range of 800 to 64000. Values below 800 do not allow sufficient sample time for the four samples; see the Electrical Characteristics table.
Figure 8-67 CONTROL1: Control Register 1 (Address = 1Eh, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
000TIMERENNUMAV[7:0]

This register configures the clock alarm pin and timer.

Bits 23:9Must be 0
Bit 8TIMEREN: Timer enable
0 = Timer module is disabled and all internal clocks are off (default after reset)
1 = Timer module is enabled
Bits 7:0NUMAV[7:0]: Number of averages
Specify an 8-bit value corresponding to the number of ADC samples to be averaged – 1.
For example, to average four ADC samples, set NUMAV[7:0] equal to 3.
The maximum number of averages is 16. Any setting of NUMAV[7:0] greater than or equal to a decimal value of 15 results in the number of averages getting set to 16.
Figure 8-68 SPARE1: SPARE1 Register For Future Use (Address = 1Fh, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
000000000000

This register is a spare register and is reserved for future use.

Bits 23:0Must be 0
Figure 8-69 TIAGAIN: Transimpedance Amplifier Gain Setting Register
(Address = 20h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 ENSEP
GAIN		 STAGE2EN1 0 0
11 10 9 8 7 6 5 4 3 2 1 0
0 STG2GAIN1[2:0] CF_LED1[4:0] RF_LED1[2:0]

This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values.

Bits 23:16Must be 0
Bit 15ENSEPGAIN: Enable separate gain mode
0 = The RF, CF values and stage 2 gain settings are the same for both the LED2 and LED1 signals; the values are specified by the bits (RF_LED2, CF_LED2, STAGE2EN2, STG2GAIN2) in the TIA_AMB_GAIN register (default after reset)
1 = The RF, CF values and stage 2 gain settings can be independently set for the LED2 and LED1 signals. The values for LED1 are specified using the bits (RF_LED1, CF_LED1, STAGE2EN1, STG2GAIN1) in the TIAGAIN register, whereas the values for LED2 are specified using the corresponding bits in the TIA_AMB_GAIN register.
Bit 14STAGE2EN1: Enable stage 2 for LED 1
0 = Stage 2 is bypassed (default after reset)
1 = Stage 2 is enabled with the gain value specified by the STG2GAIN1[2:0] bits
Bits 13:11Must be 0
Bits 10:8STG2GAIN1[2:0]: Program stage 2 gain for LED1
000 = 0 dB, or linear gain of 1 (default after reset)
001 = 3.5 dB, or linear gain of 1.5
010 = 6 dB, or linear gain of 2
011 = 9.5 dB, or linear gain of 3		100 = 12 dB, or linear gain of 4
101 = Do not use
110 = Do not use
111 = Do not use
Bits 7:3CF_LED1[4:0]: Program CF for LED1
00000 = 5 pF (default after reset)
00001 = 5 pF + 5 pF
00010 = 15 pF + 5 pF		00100 = 25 pF + 5 pF
01000 = 50 pF + 5 pF
10000 = 150 pF + 5 pF
Note that any combination of these CF settings is also supported by setting multiple bits to 1. For example, to obtain CF = 100 pF, set bits 7:3 = 01111.
Bits 2:0RF_LED1[2:0]: Program RF for LED1
000 = 500 kΩ (default after reset)
001 = 250 kΩ
010 = 100 kΩ
011 = 50 kΩ		100 = 25 kΩ
101 = 10 kΩ
110 = 1 MΩ
111 = None
Figure 8-70 TIA_AMB_GAIN: Transimpedance Amplifier and Ambient Cancellation Stage Gain Register (Address = 21h, Reset Value = 0000h)
232221201918171615141312
0000AMBDAC[3:0]FLTR
CNRSEL		STAGE2EN200
11109876543210
0STG2GAIN[2:0]CF_LED2[4:0]RF_LED2[2:0]

This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner frequency.

Bits 23:20Must be 0
Bits 19:16AMBDAC[3:0]: Ambient DAC value
These bits set the value of the cancellation current.
0000 = 0 µA (default after reset)
0001 = 1 µA
0010 = 2 µA
0011 = 3 µA
0100 = 4 µA
0101 = 5 µA
0110 = 6 µA
0111 = 7 µA		1000 = 8 µA
1001 = 9 µA
1010 = 10 µA
1011 = Do not use
1100 = Do not use
1101 = Do not use
1110 = Do not use
1111 = Do not use
Bit 15Must be 0
Bit 14STAGE2EN2: Stage 2 enable for LED 2
0 = Stage 2 is bypassed (default after reset)
1 = Stage 2 is enabled with the gain value specified by the STG2GAIN2[2:0] bits
Bits 13:11Must be 0
Bits 10:8STG2GAIN2[2:0]: Stage 2 gain setting for LED 2
000 = 0 dB, or linear gain of 1 (default after reset)
001 = 3.5 dB, or linear gain of 1.5
010 = 6 dB, or linear gain of 2
011 = 9.5 dB, or linear gain of 3
100 = 12 dB, or linear gain of 4
101 = Do not use
110 = Do not use
111 = Do not use
Bits 7:3CF_LED[4:0]: Program CF for LEDs
00000 = 5 pF (default after reset)
00001 = 5 pF + 5 pF
00010 = 15 pF + 5 pF		00100 = 25 pF + 5 pF
01000 = 50 pF + 5 pF
10000 = 150 pF + 5 pF
Note that any combination of these CF settings is also supported by setting multiple bits to 1. For example, to obtain CF = 100 pF, set D[7:3] = 01111.
Bits 2:0RF_LED[2:0]: Program RF for LEDs
000 = 500 kΩ
001 = 250 kΩ
010 = 100 kΩ
011 = 50 kΩ		100 = 25 kΩ
101 = 10 kΩ
110 = 1 MΩ
111 = None
Figure 8-71 LEDCNTRL: LED Control Register (Address = 22h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 LED_RANGE[1:0] LED1[7:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1[7:0] LED2[7:0]

This register sets the LED current range and the LED1 and LED2 drive current.

Bits 23:18Must be 0
Bits 17:16LED_RANGE[1:0]: LED range
These bits program the full-scale LED current range for Tx. Table 8-9 details the settings.
Bits 15:8LED1[7:0]: Program LED current for LED1 signal
Use these register bits to specify the LED current setting for LED1 (default after reset is 00h).
The nominal value of the LED current is given by Equation 7, where the full-scale LED current is either 0 mA or 50 mA (as specified by the LED_RANGE[1:0] register bits).
Bits 7:0LED2[7:0]: Program LED current for LED2 signal
Use these register bits to specify the LED current setting for LED2 (default after reset is 00h).
The nominal value of LED current is given by Equation 8, where the full-scale LED current is either 0 mA or 50 mA (as specified by the LED_RANGE[1:0] register bits).
Table 8-9 Full-Scale LED Current across Tx Reference Voltage Settings(1)
LED_RANGE[1:0]TX_REF = 0.25 VTX_REF = 0.5 VTX_REF = 0.75 VTX_REF = 1.0 V
IMAXVHR(2)IMAXVHRIMAXVHRIMAXVHR
00 (default after reset)50 mA0.75 V100 mA1.1 VDo not use—Do not use—
0125 mA0.7 V50 mA1.0 V75 mA1.3 V100 mA1.6 V
1050 mA0.75 V100 mA1.1 VDo not use—Do not use—
11Tx is off—Tx is off—Tx is off—Tx is off—
(1) For a 3-V to 3.6-V supply, use TX_REF = 0.25 or 0.5 V. For a 4.75-V to 5.25-V supply, use TX_REF = 0.75 V or 1.0 V.
(2) VHR refers to the headroom voltage (over and above the LED forward voltage and cable voltage drop) needed on the LED_DRV_SUP. The VHR values specified are for the H-bridge configuration. In the common anode configuration, VHR can be lower by 0.25 V.
Equation 7. GUID-ED855E7B-3283-4CFE-B510-064B6F117A67-low.gif
Equation 8. GUID-DEA6E942-D677-4D2D-800B-D270B274DA1A-low.gif
Figure 8-72 CONTROL2: Control Register 2 (Address = 23h, Reset Value = 0000h)
232221201918171615141312
000DYNAMIC10 TX_REF1TX_REF000DYNAMIC200
11109876543210
TXBRG
MOD		DIGOUT_
TRI
STATE		XTAL
DIS		 EN_
SLOW_
DIAG		000DYNAMIC3DYNAMIC4PDNTXPDNRXPDNAFE

This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.

Bits 23:21Must be 0
Bit 20DYNAMIC1
0 = Transmitter is not powered down during dynamic power-down phase
1 = Transmitter is powered down during dynamic power-down phase
Bit 19Must be 0
Bits 18:17TX_REF[1:0]: Tx reference voltage
These bits set the transmitter reference voltage. This Tx reference voltage is available on the device TX_REF pin.
00 = 0.25-V Tx reference voltage (default value after reset)
01 = 0.5-V Tx reference voltage
10 = 1.0-V Tx reference voltage
11 = 0.75-V Tx reference voltage, D3
Bits 16:15Must be 0
Bit 14DYNAMIC2
0 = Part of the ADC is not powered down during dynamic power-down phase
1 = Part of the ADC is powered down during dynamic power-down phase
Bit 11TXBRGMOD: Tx bridge mode
0 = LED driver is configured as an H-bridge (default after reset)
1 = LED driver is configured as a push-pull
Bit 10DIGOUT_TRISTATE: Tri-state bit for the ADC_RDY and DIAG_END pins
0 = ADC_RDY and DIAG_END are not tri-stated
1 = ADC_RDY and DIAG_END are tri-stated
Bit 9XTALDIS: Crystal disable mode
0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and XOUT pins
1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin
Bit 8EN_SLOW_DIAG: Fast diagnostics mode enable
0 = Fast diagnostics mode, 8 ms (default value after reset)
1 = Slow diagnostics mode, 16 ms
Bits 7:5Must be 0
Bit 4DYNAMIC3
0 = TIA is not powered down during dynamic power-down phase
1 = TIA is powered down during dynamic power-down phase
Bit 3DYNAMIC4
0 = The rest of the ADC is not powered down during dynamic power-down phase
1 = The rest of the ADC is powered down during dynamic power-down phase
Bit 2PDN_TX: Tx power-down
0 = The Tx is powered up (default after reset)
1 = Only the Tx module is powered down
Bit 1PDN_RX: Rx power-down
0 = The Rx is powered up (default after reset)
1 = Only the Rx module is powered down
Bit 0PDN_AFE: AFE power-down
0 = The AFE is powered up (default after reset)
1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks)
Figure 8-73 SPARE2: SPARE2 Register For Future Use (Address = 24h, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
000000000000

This register is a spare register and is reserved for future use.

Bits 23:0Must be 0
Figure 8-74 SPARE3: SPARE3 Register For Future Use (Address = 25h, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
000000000000

This register is a spare register and is reserved for future use.

Bits 23:0Must be 0
Figure 8-75 SPARE4: SPARE4 Register For Future Use (Address = 26h, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
000000000000

This register is a spare register and is reserved for future use.

Bits 23:0Must be 0
Figure 8-76 RESERVED1: RESERVED1 Register For Factory Use Only
(Address = 27h, Reset Value = XXXXh)
232221201918171615141312
X(1)XXXXXXXXXXX
11109876543210
XXXXXXXXXXXX
(1) X = don't care.

This register is reserved for factory use. Readback values vary between devices.

Figure 8-77 RESERVED2: RESERVED2 Register For Factory Use Only
(Address = 28h, Reset Value = XXXXh)
232221201918171615141312
X(1)XXXXXXXXXXX
11109876543210
XXXXXXXXXXXX

This register is reserved for factory use. Readback values vary between devices.

Figure 8-78 ALARM: Alarm Register (Address = 29h, Reset Value = 0000h)
232221201918171615141312
000000000000
11109876543210
000000000000

This register controls the alarm pin functionality.

Bits 23:0Must be 0
Figure 8-79 LED2VAL: LED2 Digital Sample Value Register (Address = 2Ah, Reset Value = 0000h)
232221201918171615141312
LED2VAL[23:0]
11109876543210
LED2VAL[23:0]
Bits 23:0LED2VAL[23:0]: LED2 digital value
This register contains the digital value of the latest LED2 sample converted by the ADC.
Figure 8-80 ALED2VAL: Ambient LED2 Digital Sample Value Register
(Address = 2Bh, Reset Value = 0000h)
232221201918171615141312
ALED2VAL[23:0]
11109876543210
ALED2VAL[23:0]
Bits 23:0ALED2VAL[23:0]: LED2 ambient digital value
This register contains the digital value of the latest LED2 ambient sample converted by the ADC.
Figure 8-81 LED1VAL: LED1 Digital Sample Value Register (Address = 2Ch, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
LED1VAL[23:0]
11 10 9 8 7 6 5 4 3 2 1 0
LED1VAL[23:0]
Bits 23:0LED1VAL[23:0]: LED1 digital value
This register contains the digital value of the latest LED1 sample converted by the ADC.
Figure 8-82 ALED1VAL: Ambient LED1 Digital Sample Value Register
(Address = 2Dh, Reset Value = 0000h)
232221201918171615141312
ALED1VAL[23:0]
11109876543210
ALED1VAL[23:0]
Bits 23:0ALED1VAL[23:0]: LED1 ambient digital value
This register contains the digital value of the latest LED1 ambient sample converted by the ADC.
Figure 8-83 LED2-ALED2VAL: LED2-Ambient LED2 Digital Sample Value Register
(Address = 2Eh, Reset Value = 0000h)
232221201918171615141312
LED2-ALED2VAL[23:0]
11109876543210
LED2-ALED2VAL[23:0]
Bits 23:0LED2-ALED2VAL[23:0]: (LED2 – LED2 ambient) digital value
This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted.
Note that this value is inverted when compared to waveforms shown in many publications.
Figure 8-84 LED1-ALED1VAL: LED1-Ambient LED1 Digital Sample Value Register
(Address = 2Fh, Reset Value = 0000h)
232221201918171615141312
LED1-ALED1VAL[23:0]
11109876543210
LED1-ALED1VAL[23:0]
Bits 23:0LED1-ALED1VAL[23:0]: (LED1 – LED1 ambient) digital value
This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted from it.
Note that this value is inverted when compared to waveforms shown in many publications.
Figure 8-85 DIAG: Diagnostics Flag Register (Address = 30h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 0 0 0 PD_ALM
11 10 9 8 7 6 5 4 3 2 1 0
LED_
ALM		 LED2
OPEN		 LED1
OPEN		 LEDSC OUTNSHGND OUTPSHGND PDOC PDSC INNSC
GND		 INPSC
GND		 INNSC
LED		 INPSC
LED

This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.

Bits 23:13Read only
Bit 12PD_ALM: Power-down alarm status diagnostic flag
This bit indicates the status of PD_ALM .
0 = No fault (default after reset)
1 = Fault present
Bit 11LED_ALM: LED alarm status diagnostic flag
This bit indicates the status of LED_ALM .
0 = No fault (default after reset)
1 = Fault present
Bit 10LED2OPEN: LED2 open diagnostic flag
This bit indicates that LED2 is open.
0 = No fault (default after reset)
1 = Fault present
Bit 9LED1OPEN: LED1 open diagnostic flag
This bit indicates that LED1 is open.
0 = No fault (default after reset)
1 = Fault present
This bit indicates that LED2 is open.
0 = No fault (default after reset)
1 = Fault present
Bit 8LEDSC: LED short diagnostic flag
This bit indicates an LED short.
0 = No fault (default after reset)
1 = Fault present
Bit 7OUTNSHGND: OUTN to GND diagnostic flag
This bit indicates that OUTN is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 6OUTPSHGND: OUTP to GND diagnostic flag
This bit indicates that OUTP is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 5PDOC: PD open diagnostic flag
This bit indicates that PD is open.
0 = No fault (default after reset)
1 = Fault present
Bit 4 PDSC: PD short diagnostic flag
This bit indicates a PD short.
0 = No fault (default after reset)
1 = Fault present
Bit 3INNSCGND: INN to GND diagnostic flag
This bit indicates a short from the INN pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 2INPSCGND: INP to GND diagnostic flag
This bit indicates a short from the INP pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit 1INNSCLED: INN to LED diagnostic flag
This bit indicates a short from the INN pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
Bit 0INPSCLED: INP to LED diagnostic flag
This bit indicates a short from the INP pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
Figure 8-86 CONTROL3: Control Register (Address = 31h, Reset Value = 0000h)
232221201918171615141312
00000000TX3_MODE000
11109876543210
0000000SOMI_
TRI		CLKOUT_TRICLKDIV[2:0]

This register controls the clock divider ratio.

Bits 23:16Must be 0
Bit 15TX3_MODE: Selection of third LED
This bit transitions the control from the default two LEDs (on TXP, TXN) to the third LED on TX3.
0 = LEDs on TXP, TXN are active
1 = LED on TX3 is active. Timing engine controls on TXP are transferred to TX3. Maximum current setting supported for the third LED is 50 mA.
Bits 14:5Must be 0
Bit 4SOMI_TRI: Serial data output 3-state mode
This bit determines the state of the SPISOMI output pin. In order to avoid loading the SPI bus when multiple devices are connected, this bit must be set to 1 (3-state mode) whenever the device SPI is inactive.
0 = SPISOMI output buffer is active (normal operation, default)
1 = SPISOMI output buffer is in 3-state mode
Bit 3CLKOUT_TRI: CLKOUT output 3-state mode
This bit determines the state of the CLKOUT output pin.
0 = CLKOUT buffer is active (normal operation, default)
1 = CLKOUT buffer is in 3-state mode
Bits 2:0CLKDIV[2:0]: Clock divider ratio
These bits set the ratio of the clock divider and determine the frequency of CLKOUT relative to the input clock frequency.
Table 8-10 shows the clock divider ratio settings.
Table 8-10 Clock Divider Ratio Settings
CLKDIV[2:0]DIVIDER RATIOINPUT CLOCK FREQUENCY RANGE
000Divide-by-28 MHz to 12 MHz(2)
001Do not useDo not use
010Divide-by-416 MHz to 24 MHz(2)
011Divide-by-624 MHz to 36 MHz
100Divide-by-832 MHz to 48 MHz
101Divide-by-1248 MHz to 60 MHz
110Do not useDo not use
111Divide by 1(1)4 MHz to 6 MHz
(1) When using divide-by-1, the external clock should have a duty cycle between 48% to 52%.
(2) These frequency ranges can be used when generating the clock using the crystal.
Figure 8-87 PDNCYCLESTC: PDNCYCLESTC Register (Address = 32h, Reset Value = 0000h)
23 22 21 20 19 18 17 16 15 14 13 12
0 0 0 0 0 0 0 0 PDNCYCLESTC[15:0]
11 10 9 8 7 6 5 4 3 2 1 0
PDNCYCLESTC[15:0]
Bits 23:16Must be 0
Bits 15:0PDNCYCLESTC[15:0]: Dynamic (cycle-to-cycle) power-down start count
The contents of this register can be used to position the start of the PDN_CYCLE signal with respect to the pulse repetition period (PRP). The count is specified as the number of cycles of CLKOUT. If the dynamic power-down feature is not required, then do not program this register.
Figure 8-88 PDNCYCLEENDC: PDNCYCLEENDC Register (Address = 33h, Reset Value = 0000h)
232221201918171615141312
00000000PDNCYCLEENDC[15:0]
11109876543210
PDNCYCLEENDC[15:0]
Bits 23:16Must be 0
Bits 15:0PDNCYCLEENDC[15:0]: Dynamic (cycle-to-cycle) power-down end count
The contents of this register can be used to position the end of the PDN_CYCLE signal with respect to the pulse repetition period (PRP). The count is specified as the number of cycles of CLKOUT. If the dynamic power-down feature is not required, then do not program this register.
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