米6体育平台手机版

ZHCSCL7C May 2014 – April 2021 AFE4403

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机械数据 (封装 | 引脚)

YZP|36
- MXBG349

散热焊盘机械数据 (封装 | 引脚)

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7.5 Electrical Characteristics

Minimum and maximum specifications are at T_A = –20°C to 70°C, typical specifications are at 25°C. Crystal mode enabled, detector capacitor = 50 pF differential, ADC averaging set to maximum allowed for each PRF, TX_REF voltage set to 0.5 V, and CLKOUT tri-stated, at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 3.3 V, stage 2 amplifier disabled, and f_CLK = 8 MHz, unless otherwise noted.

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT
PERFORMANCE (Full-Signal Chain)
I_{IN_FS}	Full-scale input current		R_F = 10 kΩ			50		µA
			R_F = 25 kΩ			20		µA
			R_F = 50 kΩ			10		µA
			R_F = 100 kΩ			5		µA
			R_F = 250 kΩ			2		µA
			R_F = 500 kΩ			1		µA
			R_F = 1 MΩ			0.5		µA
PRF	Pulse repetition frequency				62.5		2000	SPS
DC_PRF	PRF duty cycle						25%
CMRR	Common-mode rejection ratio		f_CM = 50 Hz and 60 Hz, LED1 and LED2 with R_SERIES = 500 kΩ, R_F = 500 kΩ			75		dB
CMRR	Common-mode rejection ratio		f_CM = 50 Hz and 60 Hz, LED1-AMB and LED2-AMB with R_SERIES = 500 kΩ, R_F = 500 kΩ			95		dB
PSRR_LED	PSRR, transmit LED driver		With respect to ripple on LED_DRV_SUP			75		dB
PSRR_Tx	PSRR, transmit control		With respect to ripple on TX_CTRL_SUP			60		dB
PSRR_Rx	PSRR, receiver		With respect to ripple on RX_ANA_SUP and RX_DIG_SUP			60		dB
	Total integrated noise current, input-referred (receiver with transmitter loop back, 0.1-Hz to 20-Hz bandwidth)		R_F = 100 kΩ, PRF = 600 Hz, duty cycle = 5%			25		pA_RMS
			R_F = 500 kΩ, PRF = 600 Hz, duty cycle = 5%			6		pA_RMS
RECEIVER FUNCTIONAL BLOCK LEVEL SPECIFICATION
	Total integrated noise current, input referred (receiver alone) over 0.1-Hz to 20-Hz bandwidth		R_F = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 25%			3.2		pA_RMS
			R_F = 500 kΩ, ambient cancellation enabled, stage 2 gain = 4, PRF = 1200 Hz, LED duty cycle = 5%			5.3		pA_RMS
I-V TRANSIMPEDANCE AMPLIFIER
G	Gain		R_F = 10 kΩ to 1 MΩ		See the Receiver Channel section for details			V/µA
	Gain accuracy					±7%
	Feedback resistance		R_F		10k, 25k, 50k, 100k, 250k, 500k, and 1M			Ω
	Feedback resistor tolerance		R_F			±20%
	Feedback capacitance		C_F		5, 10, 25, 50, 100, and 250			pF
	Feedback capacitor tolerance		C_F			±20%
	Full-scale differential output voltage					1		V
	Common-mode voltage on input pins		Set internally			0.9		V
	External differential input capacitance		Includes equivalent capacitance of photodiode, cables, EMI filter, and so forth		10		1000	pF
	Shield output voltage, V_CM		With a 1-kΩ series resistor and a 10-nF decoupling capacitor to ground		0.8	0.9	1	V
AMBIENT CANCELLATION STAGE
	Gain				0, 3.5, 6, 9.5, and 12			dB
	Current DAC range				0		10	µA
	Current DAC step size					1		µA
LOW-PASS FILTER
	Low-pass corner frequency		3-dB attenuation			500		Hz
	Pass-band attenuation, 2 Hz to 10 Hz		Duty cycle = 25%			0.004		dB
	Pass-band attenuation, 2 Hz to 10 Hz		Duty cycle = 10%			0.041		dB
	Filter settling time		After diagnostics mode			28		ms
ANALOG-TO-DIGITAL CONVERTER
	Resolution						22	Bits
	Sample rate		See the ADC Operation and Averaging Module section			4 × PRF		SPS
	ADC full-scale voltage					±1.2		V
	ADC conversion time		See the ADC Operation and Averaging Module section				PRF / 4	µs
	ADC reset time⁽²⁾				2			t_CLK
TRANSMITTER
	Output current range				Selectable, 0 to 100 (see the LEDCNTRL: LED Control Register for details)			mA
	LED current DAC error					±10%
	Output current resolution					8		Bits
	Transmitter noise dynamic range, over 0.1-Hz to 20-Hz bandwidth, TX_REF set to 0.5 V		At 25-mA output current			110		dB
			At 50-mA output current			110		dB
	Minimum sample time of LED1 and LED2 pulses					50		µs
	LED current DAC leakage current		LED_ON = 0			1		µA
	LED current DAC leakage current		LED_ON = 1			50		µA
	LED current DAC linearity		Percent of full-scale current			0.50		%
	Output current settling time (with resistive load)		From zero current to 50 mA			7		µs
	Output current settling time (with resistive load)		From 50 mA to zero current			7		µs
DIAGNOSTICS
	Duration of diagnostics state machine		Start of diagnostics after the DIAG_EN register bit is set. End of diagnostic is indicated by DIAG_END going high.			16		ms
	Open fault resistance					> 100		kΩ
	Short fault resistance					< 10		kΩ
INTERNAL OSCILLATOR
f_CLKOUT	CLKOUT frequency		With an 8-MHz crystal connected to the XIN, XOUT pins			4		MHz
	CLKOUT duty cycle					50%
	Crystal oscillator start-up time		With an 8-MHz crystal connected to the XIN, XOUT pins			200		µs
EXTERNAL CLOCK
	Maximum allowable external clock jitter		For SPO2 applications			50		ps
	Maximum allowable external clock jitter		For optical heart rate only				1000	ps
	External clock input frequency ⁽¹⁾		±2%		4	8	60	MHz
	External clock input voltage		Voltage input high (V_IH)		0.75 × RX_DIG_SUP			V
	External clock input voltage		Voltage input low (V_IL)		0.25 × RX_DIG_SUP			V
TIMING
	Wake-up time from complete power-down					1000		ms
	Wake-up time from Rx power-down					100		µs
	Wake-up time from Tx power-down					1000		ms
t_RESET	Active low RESET pulse duration					1		ms
t_DIAGEND	DIAG_END pulse duration at the completion of diagnostics					4		CLKOUT cycles
t_ADCRDY	ADC_RDY pulse duration					1		CLKOUT cycle
DIGITAL SIGNAL CHARACTERISTICS
V_IH	Logic high input voltage		AFE_ PDN, SCLK, SPISIMO, SPISTE, RESET		0.8 DVDD	> 1.3	DVDD + 0.1	V
V_IL	Logic low input voltage		AFE_ PDN, SCLK, SPISIMO, SPISTE, RESET		–0.1	< 0.4	0.2 DVDD	V
I_IN	Logic input current		0 V < V_DigitalInput < DVDD		–10		10	µA
V_OH	Logic high output voltage		DIAG_END, SPISOMI, ADC_RDY, CLKOUT		0.9 DVDD	> (RX_DIG_SUP – 0.2 V)		V
V_OL	Logic low output voltage		DIAG_END, SPISOMI, ADC_RDY, CLKOUT			< 0.4	0.1 DVDD	V
SUPPLY CURRENT
	Receiver analog supply current		RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 disabled			0.6		mA
			RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 enabled			0.7		mA
			RX_ANA_SUP = 3.0 V, with 8-MHz clock running, Rx stage 2 disabled, external clock mode			0.49		mA
	Receiver digital supply current		RX_DIG_SUP = 3.0 V			0.15		mA
	LED driver supply current		With zero LED current setting			30		µA
	Transmitter control supply current					15		µA
	Complete power-down (using the AFE_ PDN pin)		Receiver current only (RX_ANA_SUP)			3		µA
			Receiver current only (RX_DIG_SUP)			3		µA
			Transmitter current only (LED_DRV_SUP)			1		µA
			Transmitter current only (TX_CTRL_SUP)			1		µA
	Power-down Rx alone		Receiver current only (RX_ANA_SUP)			200		µA
	Power-down Rx alone		Receiver current only (RX_DIG_SUP)			150		µA
	Power-down Tx alone		Transmitter current only (LED_DRV_SUP)			2		µA
	Power-down Tx alone		Transmitter current only (TX_CTRL_SUP)			2		µA
POWER DISSIPATION
	Power-down with the AFE_PDN pin	LED_DRV_SUP	Does not include LED current.			1		µA
		TX_CTRL_SUP				1		µA
		RX_ANA_SUP				5		µA
		RX_DIG_SUP				0.1		µA
	Power-down with the PDNAFE register bit	LED_DRV_SUP	Does not include LED current.			1		µA
		TX_CTRL_SUP				1		µA
		RX_ANA_SUP				15		µA
		RX_DIG_SUP				20		µA
	Power-down Rx	LED_DRV_SUP	Does not include LED current.			30		µA
		TX_CTRL_SUP				15		µA
		RX_ANA_SUP				200		µA
		RX_DIG_SUP				150		µA
	Power-down Tx	LED_DRV_SUP	Does not include LED current.			2		µA
		TX_CTRL_SUP				2		µA
		RX_ANA_SUP				600		µA
		RX_DIG_SUP				150		µA
	After reset, with 8-MHz clock running	LED_DRV_SUP	Does not include LED current.			30		µA
		TX_CTRL_SUP				15		µA
		RX_ANA_SUP				600		µA
		RX_DIG_SUP				150		µA
	With stage 2 mode enabled and 8-MHz clock running	LED_DRV_SUP	Does not include LED current.			30		µA
		TX_CTRL_SUP				15		µA
		RX_ANA_SUP				700		µA
		RX_DIG_SUP				150		µA
	Dynamic power-down mode enabled	LED_DRV_SUP	Does not include LED current.	PRF = 100 Hz, PDN_CYCLE duration = 8 ms		7		µA
		TX_CTRL_SUP				5		µA
		RX_ANA_SUP				205		µA
		RX_DIG_SUP				150		µA

(1) Refer to the CLKDIV[2:0] register bits for a detailed list of input clock frequencies that are supported.

(2) A low ADC reset time can result in a small component of the LED signal leaking into the ambient phase. With an ADC reset of two clock cycles, a –60-dB leakage is expected. In many cases, this leakage does not affect system performance. However, if this crosstalk must be completely eliminated, a longer ADC reset time of approximately six clock cycles is recommended for t₂₂, t₂₄, t₂₆, and t₂₈ in Figure 8-13.