See Figure 8-10 for a timing diagram detailing the various timing edges that are programmable using the timer module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit counter (running off of the 4-MHz clock) to set the time-base.

All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to 0.

NOTE: Programmable edges are shown in blue and red.

Figure 8-10 AFE Control Signals

For the timing signals in Figure 8-6, the start and stop edge positions are programmable with respect to the PRF period. Each signal uses a separate timer compare module that compares the counter value with preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI interface.

After the counter value has exceeded the stop reference value, the output signal is set. When the counter value equals the stop reference value, the output signal is reset. Figure 8-11 shows a diagram of the timer compare register. With a 4-MHz clock, the edge placement resolution is 0.25 µs.

Figure 8-11 Compare Register

The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four sets of start and stop registers to control the ADC conversion signal, as shown in Figure 8-12.

Figure 8-12 Timer Module