In this mode, the ADC outputs a digital sample one time for every 50 µs. Consider a case where the ADC Reset signals are positioned at 25%, 50%, 75%, and 100% (or 0%) points in the pulse repetition period. At each rising edge of the ADC reset signal, one ADC conversion value is written into the result registers sequentially as follows (see Figure 8-28):

• At the 25% reset signal, the first ADC conversion sample is written to register 2Ah (Decimal address = 42).
• At the 50% reset signal, the second ADC conversion sample is written to register 2Bh (Decimal address = 43).
• At the 75% reset signal, the third ADC conversion sample is written to register 2Ch (Decimal address = 44).
• At the next 0% reset signal, the fourth ADC conversion sample is written to register 2Dh (Decimal address = 45).
• Every time the registers 2Ah and 2Bh are updated, the contents of the difference register 2Eh is updated. Similarly, every time the registers 2Ch and 2Dh are updated, the contents of the difference register 2Fh is updated.

The time window between the ADC_RDY (first ADC Reset) and the second ADC Reset represents the window where the contents of all the 6 registers correspond to the samples of the four conversion phases from the previous pulse repetition period.

The MCU could either read all of these registers during this time window, or could read each register separately in the time window where its contents are stable.