9.2.2.1.1 LNA Input Coupling and Decoupling

The LNA closed-loop architecture is internally compensated for maximum stability without the need of external compensation components. The LNA inputs are biased at 2.4 V and AC coupling is required. Figure 99 shows a typical input configuration. C_IN is the input AC coupling capacitor. C_ACT is a part of the active termination feedback path. Even if the active termination is not used, the C_ACT is required for the clamp functionality. The recommended values for C_ACT is ≥1 µF and C_IN is ≥0.1 µF. A pair of clamping diodes is commonly placed between the T/R switch and the LNA input. Schottky diodes with suitable forward drop voltage (for example: the BAT754/54 series, the BAS40 series, the MMBD7000 series, or similar) can be considered depending on the transducer echo amplitude.

Figure 99. LNA Input Configurations

This architecture minimizes any loading of the signal source that may lead to a frequency-dependent voltage divider. The closed-loop design yields low offsets and offset drift. C_BYPASS (≥0.015 µF) is used to set the HPF cut-off frequency and decouple the complementary input. Its cut-off frequency is inversely proportional to the C_BYPASS value. The HPF cut-off frequency can be adjusted through the register 59[3:2] Table 27 lists. Low-frequency signals at T/R switch output, such as signals with slow ringing, can be filtered out. In addition, the HPF can minimize system noise from DC-DC converters, pulse repetition frequency (PRF) trigger, and frame clock. Most ultrasound systems’ signal-processing unit includes digital HPFs or band-pass filters (BPFs) in FPGAs or ASICs. Further noise suppression can be achieved in these blocks. In addition, a digital HPF is available in the AFE5809 ADC. If low-frequency signal detection is desired in some applications, the LNA HPF can be disabled.

CM_BYP and VHIGH pins, which generate internal reference voltages, must be decoupled with ≥1-µF capacitors. Bigger bypassing capacitors (>2.2 µF) may be beneficial if low-frequency noise exists in the system.

9.2.2.1.2 LNA Noise Contribution

The noise specification is critical for LNA and it determines the dynamic range of the entire system. The LNA of the AFE5809 device achieves low power and an exceptionally low-noise voltage of 0.63 nV/√Hz, and a low current noise of 2.7 pA/√Hz.

Typical ultrasonic transducer’s impedance, R_S, varies from tens of Ω to several hundreds of Ω. Voltage noise is the dominant noise in most cases; however, the LNA current noise flowing through the source impedance (R_S) generates additional voltage noise.

Equation 12.

The AFE5809 device achieves low-noise figure (NF) over a wide range of source resistances as shown in Figure 32, Figure 33, and Figure 34.

9.2.2.1.3 Active Termination

In ultrasound applications, signal reflection exists due to long cables between the transducer and system. The reflection results in extra ringing added to echo signals in PW mode. Because the axial resolution depends on echo signal length, such ringing effect can degrade the axial resolution. Therefore, either passive termination or active termination is preferred if good axial resolution is desired. Figure 100 shows three termination configurations.

Figure 100. Termination Configurations

Under the no termination configuration, the input impedance of the AFE5809 is about 6 kΩ (8 K//20 pF) at 1 MHz. Passive termination requires external termination resistor R_t, which contributes to additional thermal noise.

The LNA supports active termination with programmable values, as shown in Figure 101 .

Figure 101. Active Termination Implementation

The AFE5809 device has four pre-settings 50, 100, 200, and 400 Ω, which are configurable through the registers. Other termination values can be realized by setting the termination switches shown in Figure 101. Register [52] is used to enable these switches. The input impedance of the LNA under the active termination configuration approximately follows:

Equation 13.

Table 5 lists the LNA R_INs under different LNA gains. System designers can achieve fine tuning for different probes.

The equivalent input impedance is given by Equation 14 where R_IN (8 kΩ) and C_IN (20 pF) are the input resistance and capacitance of the LNA.

Equation 14.

Therefore, the Z_IN is frequency dependent, and it decreases as frequency increases as shown in Figure 10. Because 2 to 10 MHz is the most commonly used frequency range in medical ultrasound, this rolling-off effect does not impact system performance greatly. Active termination can be applied to both CW and TGC modes. Because each ultrasound system includes multiple transducers with different impedances, the flexibility of impedance configuration is a great plus.

Figure 32, Figure 33, and Figure 34 show the NF under different termination configurations. It indicates that no termination achieves the best noise figure; active termination adds less noise than passive termination. Thus, termination topology should be carefully selected based on each use scenario in ultrasound.

9.2.2.1.4 LNA Gain Switch Response

The LNA gain is programmable through SPI. The gain switching time depends on the SPI speed as well as the LNA gain response time. During the switching, glitches might occur and they can appear as artifacts in images. In addition, the signal chain needs about 14 µs to settle after the LNA gain change. Thus, LNA gain switching may not be preferred when switching time or settling time for the signal chain is limited.

Table 28. V_CNTLP – V_CNTLM vs Gain Under Different LNA and PGA Gain Settings (Low-Noise Mode)

9.2.2.3.1 CW Summing Amplifier

To simplify CW system design, a summing amplifier is implemented in the AFE5809 to sum and convert 8-channel mixer current outputs to a differential voltage output. Low noise and low power are achieved in the summing amplifier while maintaining the full dynamic range required in CW operation.

This summing amplifier has five internal gain adjustment resistors which can provide 32 different gain settings (register 54[4:0], Figure 101 and Table 8). System designers can easily adjust the CW path gain depending on signal strength and transducer sensitivity. For any other gain values, an external resistor option is supported. The gain of the summation amplifier is determined by the ratio between the 500-Ω resistors after LNA and the internal or external resistor network R_EXT/INT. Thus, the matching between these resistors plays a more important role than absolute resistor values. Better than 1% matching is achieved on chip. Due to process variation, the absolute resistor tolerance could be higher. If external resistors are used, the gain error between I/Q channels or among multiple AFEs may increase. TI recommends using internal resistors to set the gain to achieve better gain matching (across channels and multiple AFEs). With the external capacitor C_EXT , this summing amplifier has first-order LPF response to remove high-frequency components from the mixers, such as 2f0±fd. Its cut-off frequency is determined by:

Equation 15.

When different gain is configured through Register 54[4:0], the LPF response varies as well.

Figure 104. CW Summing Amplifier Block Diagram

Multiple AFE5809 devices are usually used in parallel to expand CW beamformer channel count. The AFE5809 CW's voltage outputs can be summed and filtered externally further to achieve desired gain and filter response. AC-coupling capacitors C_AC are required to block the DC component of the CW carrier signal. C_AC can vary from 1 to 10 μF depending on the desired low-frequency Doppler signal from slow blood flow. Multiple AFE5809s’ I/Q outputs can be summed together with a low-noise differential amplifiers before 16, 18-bit differential audio ADCs. The TI ultralow noise differential precision amplifier OPA1632 and THS4130 are suitable devices.

Figure 106 shows an alternative current summing circuit. However, this circuit only achieves good performance when a lower-noise operational amplifier is available compared to the AFE5809's internal summing differential amplifier.

Figure 105. CW Circuit With Multiple AFE5809s (Voltage Output Mode)

Figure 106. CW Circuit With Multiple AFE5809s (Current Output Mode, CM_BYP=1.5 V)

The CW I/Q channels are well matched internally to suppress image frequency components in the Doppler spectrum. Low-tolerance components and precise operational amplifiers should be used for achieving good matching in the external circuits as well.

9.2.2.3.2 CW Clock Selection

The AFE5809 device can accept differential LVDS, LVPECL, and other differential clock inputs as well as single-ended CMOS clock. An internally generated VCM of 2.5 V is applied to CW clock inputs, that is, CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X. Because this 2.5-V VCM is different from the one used in standard LVDS or LVPECL clocks, AC coupling is required between clock drivers and the AFE5809 CW clock inputs. When the CMOS clock is used, CLKM_1X and CLKM_16X should be tied to ground. Figure 107 shows common clock configurations. TI recommends appropriate termination to achieve good signal integrity.

Figure 107. Clock Configurations

The combination of the clock noise and the CW path noise can degrade the CW performance. The internal clocking circuit is designed for achieving excellent phase noise required by CW operation. The phase noise of the AFE5809 CW path is better than 155 dBc/Hz at 1-kHz offset. Consequently, the phase noise of the mixer clock inputs needs to be better than 155 dBc/Hz.

In the 16/8/4 × ƒ_cw operations modes, low phase noise clock is required for 16, 8, 4 × ƒ_cw clocks (that is, CLKP_16X/ CLKM_16X pins) to maintain good CW phase noise performance. The 1 × ƒ_cw clock (that is, CLKP_1X/ CLKM_1X pins) is only used to synchronize the multiple AFE5809 chips and is not used for demodulation. Thus, 1 × ƒ_cw clock’s phase noise is not a concern. However, in the 1 × ƒ_cw operation mode, low-phase noise clocks are required for both CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X pins because both of them are used for mixer demodulation. In general, a higher slew rate clock has lower phase noise; thus, clocks with high amplitude and fast slew rate are preferred in CW operation. In the CMOS clock mode, a 5-V CMOS clock can achieve the highest slew rate.

Clock phase noise can be improved by a divider as long as the divider’s phase noise is lower than the target phase noise. The phase noise of a divided clock can be improved approximately by a factor of 20logN dB where N is the dividing factor of 16, 8, or 4. If the target phase noise of mixer LO clock 1 × ƒ_cw is 160 dBc/Hz at 1 kHz off carrier, the 16 × ƒ_cw clock phase noise should be better than 160 – 20log16 = 136 dBc/Hz. TI’s jitter cleaners LMK048X/CDCM7005/CDCE72010 exceed this requirement and can be selected for the AFE5809. In the 4×/1× modes, higher-quality input clocks are expected to achieve the same performance because N is smaller. Thus, the 16× mode is a preferred mode because it reduces the phase noise requirement for system clock design. In addition, the phase delay accuracy is specified by the internal clock divider and distribution circuit. Note in the 16× operation mode, the CW operation range is limited to 8 MHz due to the 16× CLK. The maximum clock frequency for the 16× CLK is 128 MHz. In the 8×, 4×, and 1× modes, higher CW signal frequencies up to 15 MHz can be supported with small degradation in performance, for example, the phase noise is degraded by 9 dB at 15 MHz, compared to 2 MHz.

As the channel number in a system increases, clock distribution becomes more complex. It is not preferred to use one clock driver output to drive multiple AFEs because the clock buffer’s load capacitance increases by a factor of N. As a result, the falling and rising time of a clock signal is degraded. A typical clock arrangement for multiple AFE5809 devices is shown in Figure 108. Each clock buffer output drives one AFE5809 device to achieve the best signal integrity and fastest slew rate, that is, better phase noise performance. When clock phase noise is not a concern, for example, the 1 × ƒ_cw clock in the 16, 8, 4 × ƒ_cw operation modes, one clock driver output may excite more than one AFE5809 device. Nevertheless, special considerations should be applied in such a clock distribution network design. In typical ultrasound systems, it is preferred that all clocks are generated from a same clock source, such as 16 × ƒ_cw , 1 × ƒ_cw clocks, audio ADC clocks, RF ADC clock, pulse repetition frequency signal, frame clock, and so on. By doing this, interference due to clock asynchronization can be minimized.

Figure 108. CW Clock Distribution

9.2.2.3.3 CW Supporting Circuits

As a general practice in CW circuit design, in-phase and quadrature channels should be strictly symmetrical by using well-matched layout and high-accuracy components.

In systems, additional high-pass wall filters (20 to 500 Hz) and low-pass audio filters (10 to 100 kHz) with multiple poles are usually needed. Because the CW Doppler signal ranges from 20 Hz to 20 kHz, noise under this range is critical. Consequently, low-noise audio operational amplifiers are suitable to build these active filters for CW post-processing, that is, OPA1632 or OPA2211. To find more filter design techniques, see www.ti.com. For the TI active filter design tool, see www.ti.com/filterdesigner.

The filtered audio CW I/Q signals are sampled by audio ADCs and processed by DSP or PC. Although CW signal frequency is from 20 Hz to 20 kHz, higher sampling rate ADCs are still preferred for further decimation and SNR enhancement. Due to the large dynamic range of CW signals, high resolution ADCs (≥16 bit) are required, such as ADS8413 (2 MSPS, 16-bit, 92-dBFS SNR) and ADS8472 (1 MSPS, 16-bit, 95-dBFS SNR). ADCs for in-phase and quadrature-phase channels must be strictly matched, not only amplitude matching but also phase matching, to achieve the best I/Q matching. In addition, the in-phase and quadrature ADC channels must be sampled simultaneously.

9.2.2.5.1 ADC Clock Configurations

To ensure that the aperture delay and jitter are the same for all channels, the AFE5809 uses a clock tree network to generate individual sampling clocks for each channel. The clock, for all the channels, are matched from the source point to the sampling circuit of each of the eight internal ADCs. The variation on this delay is described in the aperture delay parameter of the output interface timing. Its variation is given by the aperture jitter number of the same table.

Figure 109. ADC Clock Distribution Network

The AFE5809 ADC clock input can be driven by differential clocks (sine wave, LVPECL, or LVDS) or singled clocks (LVCMOS) similar to CW clocks as shown in Figure 107. In the single-end case, TI recommends that the use of low jitter square signals (LVCMOS levels, 1.8-V amplitude). See TI document SLYT075 for further details on the theory.

The jitter cleaner CDCM7005 or CDCE72010 is suitable to generate the AFE5809’s ADC clock and ensure the performance for the14-bit ADC with 77-dBFS SNR. Figure 109 shows a clock distribution network.

9.2.2.5.2 ADC Reference Circuit

The ADC’s voltage reference can be generated internally or provided externally. When the internal reference mode is selected, the REFP/M become output pins and should be floated. When 3[15] = 1 and 1[13] = 1, the device is configured to operate in the external reference mode in which the VREF_IN pin should be driven with a 1.4-V reference voltage and REFP/M must be left open. Because the input impedance of the VREF_IN is high, no special drive capability is required for the 1.4-V voltage reference

The digital beam-forming algorithm in an ultrasound system relies on gain matching across all receiver channels. A typical system would have about 12 octal AFEs on the board. In such a case, it is critical to ensure that the gain is matched, essentially requiring the reference voltages seen by all the AFEs to be the same. Matching references within the eight channels of a chip is done by using a single internal reference voltage buffer. Trimming the reference voltages on each chip during production ensures that the reference voltages are well-matched across different chips. When the external reference mode is used, a solid reference plane on a PCB can ensure minimal voltage variation across devices. More information on voltage reference design can be found in the document SLYT339.

The dominant gain variation in the AFE5809 comes from the VCA gain variation. The gain variation contributed by the ADC reference circuit is much smaller than the VCA gain variation. Hence, in most systems, using the ADC internal reference mode is sufficient to maintain good gain matching among multiple AFE5809s. In addition, the internal reference circuit without any external components achieves satisfactory thermal noise and phase noise performance.