8.3.1 LNA

In many high-gain systems, a LNA is critical to achieve overall performance. Using a new proprietary architecture, the LNA in the AFE5809 device delivers exceptional low-noise performance, while operating on a low-quiescent current compared to CMOS-based architectures with similar noise performance. The LNA performs single-ended input to differential output voltage conversion. It is configurable for a programmable gain of 24, 18, or 12 dB and its input-referred noise is only 0.63, 0.7, or 0.9 nV/√Hz, respectively. Programmable gain settings result in a flexible linear input range up to 1 Vpp, realizing high-signal handling capability demanded by new transducer technologies. A larger input signal can be accepted by the LNA; however, the signal can be distorted because it exceeds the LNA’s linear operation region. Combining the low noise and high-input range, the device consequently achieves a wide-input dynamic range for supporting the high demands from various ultrasound imaging modes.

The LNA input is internally biased at approximately 2.4 V; the signal source should be AC-coupled to the LNA input by an adequately-sized capacitor, for example ≥0.1 µF. To achieve low DC offset drift, the AFE5809 device incorporates a DC offset correction circuit for each amplifier stage. To improve the overload recovery, an integrator circuit is used to extract the DC component of the LNA output and then fed back to the LNA’s complementary input for DC offset correction. This DC offset correction circuit has a high-pass response and can be treated as a HPF. The effective corner frequency is determined by the capacitor C_BYPASS connected at INM. With larger capacitors, the corner frequency is lower. For stable operation at the highest HP filter cut-off frequency, a ≥15-nF capacitor can be selected. This corner frequency scales almost linearly with the value of the C_BYPASS. For example, 15 nF gives a corner frequency of approximately 100 kHz, while 47 nF can give an effective corner frequency of 33 kHz. The DC offset correction circuit can also be disabled or enabled through register 52[12]. A large capacitor like 1 µF can be used for setting low corner frequency (<2 kHz) of the LNA DC offset correction circuit. Figure 59 shows the frequency responses for low-frequency applications.

The AFE5809 device can be terminated passively or actively. Active termination is preferred in ultrasound applications for reducing reflection from mismatches and achieving better axial resolution without degrading noise figure too much. Active termination values can be preset to 50, 100, 200, and 400 Ω; other values also can be programmed by users through register 52[4:0]. A feedback capacitor is required between ACTx and the signal source as Figure 62 shows. On the active termination path, a clamping circuit is also used to create a low-impedance path when overload signal is seen by the AFE5809 device. The clamp circuit limits large input signals at the LNA inputs and improves the overload recovery performance of the AFE5809 device. The clamp level can be set to 350 mVpp, 600 mVpp, or 1.15 Vpp automatically depending on the LNA gain settings when register 52[10:9] = 0. Other clamp voltages, such as 1.15 Vpp, 0.6 Vpp, and 1.5 Vpp, are also achievable by setting register 52[10:9]. This clamping circuit is also designed to obtain good pulse inversion performance and reduce the impact from asymmetric inputs.

Figure 62. AFE5809 LNA With DC Offset Correction Circuit

8.3.2 Voltage-Controlled Attenuator

The voltage-controlled attenuator is designed to have a linear-in-dB attenuation characteristic; that is, the average gain loss in dB (refer to Figure 2) is constant for each equal increment of the control voltage (VCNTL) as shown in Figure 63. A differential control structure is used to reduce common mode noise. Figure 63 and Figure 64 show a simplified attenuator structure.

The attenuator is essentially a variable voltage divider that consists of the series input resistor (RS) and seven shunt FETs placed in parallel and controlled by sequentially activated clipping amplifiers (A1 through A7). VCNTL is the effective difference between VCNTLP and VCNTLM. Each clipping amplifier can be understood as a specialized voltage comparator with a soft transfer characteristic and well-controlled output limit voltage. Reference voltages V1 through V7 are equally spaced over the 0- to 1.5-V control voltage range. As the control voltage increases through the input range of each clipping amplifier, the amplifier output rises from a voltage where the FET is nearly OFF to VHIGH where the FET is completely ON. As each FET approaches its ON state and the control voltage continues to rise, the next clipping amplifier/FET combination takes over for the next portion of the piecewise-linear attenuation characteristic. Thus, low control voltages have most of the FETs turned OFF, producing minimum signal attenuation. Similarly, high control voltages turn the FETs ON, leading to maximum signal attenuation. Therefore, each FET acts to decrease the shunt resistance of the voltage divider formed by RS and the parallel FET network.

Additionally, a digitally-controlled TGC mode is implemented to achieve better phase-noise performance in the AFE5809 device. The attenuator can be controlled digitally instead of the analog control voltage, V_CNTL. This mode can be set by the register bit 59[7]. The variable voltage divider is implemented as a fixed series resistance and FET as the shunt resistance. Each FET can be turned on by connecting the switches SW1 through SW7. Turning on each of the switches can give approximately 6 dB of attenuation. This can be controlled by the register bits 59[6:4]. This digital control feature can eliminate the noise from the V_CNTL circuit and ensure better SNR and phase noise for the TGC path.

Figure 63. Simplified Voltage-Controlled Attenuator (Analog Structure)

Figure 64. Simplified Voltage-Controlled Attenuator (Digital Structure)

The voltage-controlled attenuator’s noise follows a monotonic relationship to the attenuation coefficient. At higher attenuation, the input-referred noise is higher and vice-versa. The attenuator’s noise is then amplified by the PGA and becomes the noise floor at ADC input. In the attenuator’s high-attenuation operating range, that is V_CNTL is high, the attenuator’s input noise may exceed the LNA output noise; the attenuator then becomes the dominant noise source for the following PGA stage and ADC. Therefore, the attenuator noise should be minimized compared to the LNA output noise. The AFE5809 attenuator is designed for achieving very-low noise even at high attenuation (low channel gain) and realizing better SNR in near field. Table 1 lists the input referred noise for different attenuations.

8.3.3 PGA

After the voltage-controlled attenuator, a PGA can be configured as 24 or 30 dB with a constant-input referred noise of 1.75 nV/rtHz. The PGA structure consists of a differential voltage-to-current converter with programmable gain, clamping circuits, a transimpedance amplifier with a programmable LPF, and a DC offset correction circuit. Figure 65 shows its simplified block diagram.

Figure 65. Simplified Block Diagram of PGA

Low input noise is always preferred in a PGA, and its noise contribution should not degrade the ADC SNR too much after the attenuator. At the minimum attenuation (used for small input signals), the LNA noise dominates; at the maximum attenuation (large input signals), the PGA and ADC noise dominates. Thus, 24-dB gain of PGA achieves better SNR as long as the amplified signals can exceed the noise floor of the ADC.

The PGA clamping circuit can be enabled (register 51) to improve the overload recovery performance of the AFE. If the user measures the standard deviation of the output just after overload, for 0.5 V V_CNTL, it is about 3.2 LSBs in normal case, that is, the output is stable in about 1 clock cycle after overload. With the clamp disabled, the value approaches 4 LSBs meaning a longer time duration before the output stabilizes; however, with the clamp enabled, there will be degradation in HD3 for PGA output levels >–2 dBFS. For example, for a –2-dBFS output level, the HD3 degrades by approximately 3 dB. To maximize the output dynamic range, the maximum PGA output level can be above 2 Vpp even with the clamp circuit enabled; the ADC in the AFE5809 device has excellent overload recovery performance to detect small signals right after the overload.

The AFE5809 device integrates an anti-aliasing filter in the form of a programmable LPF in the transimpedance amplifier. The LPF is designed as a differential, active, third-order filter with Butterworth characteristics and a typical 18 dB per octave roll-off. Programmable through the serial interface, the –1-dB frequency corner can be set to one of 10, 15, 20, and 30 MHz. The filter bandwidth is set for all channels simultaneously.

A selectable DC offset correction circuit is implemented in the PGA as well. This correction circuit is similar to the one used in the LNA. It extracts the DC component of the PGA outputs and feeds back to the PGA complementary inputs for DC offset correction. This DC offset correction circuit also has a high-pass response with a cut-off frequency of 80 kHz.

8.3.4 ADC

The ADC of the AFE5809 device employs a pipelined converter architecture that consists of a combination of multi-bit and single-bit internal stages. Each stage feeds its data into the digital error correction logic, ensuring excellent differential linearity and no missing codes at the 14-bit level. The 14 bits given out by each channel are serialized and sent out on a single pair of pins in LVDS format. All eight channels of the AFE5809 device operate from a common input clock (CLKP/M). The sampling clocks for each of the eight channels are generated from the input clock using a carefully matched clock buffer tree. The 14× clock required for the serializer is generated internally from the CLKP/M pins. A 7× and 1× clock are also given out in LVDS format, along with the data, to enable easy data capture. The AFE5809 device operates from internally-generated reference voltages that are trimmed to improve the gain matching across devices. The nominal values of REFP and REFM are 1.5 and 0.5 V, respectively. Alternatively, the device also supports an external reference mode that can be enabled using the serial interface.

Using serialized LVDS transmission has multiple advantages, such as a reduced number of output pins (saving routing space on the board), reduced power consumption, and reduced effects of digital-noise coupling to the analog circuit inside the AFE5809 device.

8.3.5 Continuous-Wave (CW) Beamformer

CWD is a key function in mid-end to high-end ultrasound systems. Compared to the TGC mode, the CW path needs to handle high dynamic range along with strict phase-noise performance. CW beamforming is often implemented in analog domain due to the strict requirements. Multiple beamforming methods are implemented in ultrasound systems, including passive delay line, active mixer, and passive mixer. Among all of them, the passive mixer approach achieves optimized power and noise. It satisfies the CW processing requirements, such as wide dynamic range, low phase noise, accurate gain and phase matching.

Figure 66 and Figure 67 show a simplified CW path block diagram and an in-phase or quadrature (I/Q) channel block diagram, respectively. Each CW channel includes a LNA, a voltage-to-current converter, a switch-based mixer, a shared summing amplifier with a LPF, and clocking circuits.

All blocks include well-matched in-phase and quadrature channels to achieve good image frequency rejection as well as beamforming accuracy. As a result, the image rejection ratio from an I/Q channel is better than –46 dBc, which is desired in ultrasound systems.

Figure 66. Simplified Block Diagram of CW Path

Note: The approximately 10- to 15-Ω resistors at CW_AMPINM/P are due to internal IC routing and can create slight attenuation.

Figure 67. Complete In-Phase or Quadrature-Phase Channel

The CW mixer in the AFE5809 device is passive and switch based; a passive mixer adds less noise than an active mixer. It achieves good performance at low power. Figure 68 and the equations describe the principles of mixer operation, where Vi(t), Vo(t), and LO(t) are input, output, and local oscillator (LO) signals for a mixer respectively. The LO(t) is square-wave based and includes odd harmonic components, as shown in Equation 1.

Figure 68. Block Diagram of Mixer Operation

Equation 1.

From Equation 1, the third-order and fifth-order harmonics from the LO can interface with the third-order and fifth-order harmonic signals in the Vi(t), or the noise around the third-order and fifth-order harmonics in the Vi(t). Therefore, the mixer’s performance is degraded. To eliminate this side effect due to the square-wave demodulation, a proprietary harmonic-suppression circuit is implemented in the AFE5809 device. The third- and fifth-harmonic components from the LO can be suppressed by over 12 dB. Thus, the LNA output noise around the third-order and fifth-order harmonic bands is not down-converted to base band. Hence, the device achieves better noise figure. The conversion loss of the mixer is about –4 dB, which is derived from .

The mixed current outputs of the eight channels are summed together internally. An internal low-noise operational amplifier is used to convert the summed current to a voltage output. The internal summing amplifier is designed to accomplish low-power consumption, low noise, and ease of use. CW outputs from multiple AFE5809 devices can be further combined on system board to implement a CW beamformer with more than eight channels. See Typical Application for more detailed information.

Multiple clock options are supported in the AFE5809 CW path. Two CW clock inputs are required: N × ƒ_cw clock and 1 × ƒ_cw clock, where ƒ_cw is the CW transmitting frequency and N could be 16, 8, 4, or 1. Users have the flexibility to select the most convenient system clock solution for the AFE5809 device. In the 16 × ƒ_cw and 8 × ƒ_cw modes, the third- and fifth-harmonic suppression feature can be supported. Thus, the 16 × ƒ_cw and 8 × ƒ_cw modes achieve better performance than the 4 × ƒ_cw and 1 × ƒ_cw modes.

8.3.5.1 16 × ƒ_cw Mode

The 16 × ƒ_cw mode achieves the best phase accuracy compared to other modes. It is the default mode for CW operation. In this mode, 16 × ƒ_cw and 1 × ƒ_cw clocks are required. 16 × ƒ_cw generates LO signals with 16 accurate phases. Multiple AFE5809 devices can be synchronized by the 1 × ƒ_cw , that is LO signals in multiple AFEs can have the same starting phase. The phase noise specification is critical only for 16× clock. The 1× clock is for synchronization only and does not require low phase noise. See the phase noise requirement in Typical Application.

Figure 69 shows the top-level clock distribution diagram. Each mixer's clock is distributed through a 16 × 8 cross-point switch. The inputs of the cross-point switch are 16 different phases of the 1× clock. TI recommends aligning the rising edges of the 1 × ƒ_cw and 16 × ƒ_cw clocks.

The cross-point switch distributes the clocks with appropriate phase delay to each mixer. For example, Vi(t) is a received signal with a delay of , a delayed LO(t) should be applied to the mixer to compensate for the delay. Thus a 22.5⁰ delayed clock, that is , is selected for this channel. The mathematic calculation is expressed in the following equations:

Equation 2.

Vo(t) represents the demodulated Doppler signal of each channel. When the Doppler signals from N channels are summed, the signal-to-noise ratio improves.

Figure 69.

Figure 70. 1× and 16× CW Clock Timing

8.3.5.2 8 × ƒ_cw and 4 × ƒ_cw Modes

8 × ƒ_cw and 4 × ƒ_cw modes are alternative modes when a higher frequency clock solution (that is 16 × ƒ_cw clock) is not available in system. Figure 71 shows a block diagram of these two modes.

Good phase accuracy and matching are also maintained. Quadrature clock generator is used to create in-phase and quadrature clocks with exactly 90° phase difference. The only difference between 8 × ƒ_cw and 4 × ƒ_cw modes is the accessibility of the third- and fifth-harmonic suppression filter. In the 8 × ƒ_cw mode, the suppression filter can be supported. In both modes, phase delay resolution is achieved by weighting the in-phase and quadrature paths correspondingly. For example, if a delay of or 22.5° is targeted, the weighting coefficients should follow Equation 3, assuming I_in and Q_in are sin(ω₀t) and cos(ω₀t) respectively.

Equation 3.

Therefore, after I/Q mixers, phase delay in the received signals is compensated. The mixers’ outputs from all channels are aligned and added linearly to improve the signal-to-noise ratio. It is preferred to have the 4 × ƒ_cw or 8 × ƒ_cw and 1 × ƒ_cw clocks both aligned at the rising edge.

Figure 71. 8 × ƒ_cw and 4 × ƒ_cw Block Diagram

Figure 72. 8 × ƒ_cw and 4 × ƒ_cw Timing Diagram

8.3.5.3 1 × ƒ_cw Mode

The 1 × ƒ_cw mode requires in-phase and quadrature clocks with low phase noise specifications. The phase delay resolution is also achieved by weighting the in-phase and quadrature signals as described in the 8 × ƒ_cw and 4 × ƒ_cw modes.

Figure 73. Block Diagram of 1 x ƒ_cw mode

8.3.6 Digital I/Q Demodulator

The AFE5809 device also includes a digital in-phase and quadrature (I/Q) demodulator and a low-pass decimation filter. The main purpose of the demodulation block is to reduce the LVDS data rate and improve overall system power efficiency. The I/Q demodulator accepts ADC output with up to 65-MSPS sampling rate and 14-bit resolution. For example, after digital demodulation and 4× decimation filtering, the data rate for either in-phase or quadrature output is reduced to 16.25 MSPS, and the data resolution is improved to 16 bits consequently. Hence, the overall LVDS trace reduction can be a factor of 2. This demodulator can be bypassed and powered down completely if it is not needed.

The digital demodulator block given in the AFE5809 device is designed to do down-conversion followed by decimation. The top-level block is divided into two exactly similar blocks: (1) subchip0 and (2) subchip1. Both subchips share four channels each, that is, subchip0 (ADC.1, ADC.2, ADC.3, and ADC.4) and subchip1 (ADC.5, ADC.6, ADC.7, and ADC.8).

Figure 74. Subchip

The following four functioning blocks are given in each demodulator. Every block can be bypassed.

• DC removal block
• Down conversion
• Decimator
• Channel multiplexing

Figure 75. Digital Demodulator Block

1. DC removal block is used to remove DC offset. An offset value can be given to a specific register.
2. Down conversion or demodulation of signal is done by multiplying signal by cos(ω₀t) and by –sin(ω₀t) to give out I phase and Q phase, respectively. cos(ωt) and –sin(ωt) are 14-bit wide plus a sign bit. ω = 2πƒ, ƒ can be set with resolution Fs / 2¹⁶, where Fs is the ADC sampling frequency.

NOTE

The digital demodulator is based on a conventional down converter, that is, –sin(ω₀t) is used for Q phase.

3. The decimator block has two functions: decimation filter and down sampler. Decimation filter is a variable coefficient symmetric FIR filter and its coefficients can be given using coefficient RAM. Number of taps of FIR filter is 16× decimation factor (M). For decimation factor of M, 8M coefficients must be stored in the coefficient bank. Each coefficient is 14-bit wide. Down-sampler gives out 1 sample followed by M – 1 samples zeros.
4. In Figure 76, channel multiplexing is implemented for flexible data routing:

Figure 76. Channel Multiplexing

8.3.7 Equivalent Circuits

Figure 77. Equivalent Circuits of LNA Inputs

Figure 78. Equivalent Circuits of V_CNTLP/M

Figure 79. Equivalent Circuits of Clock Inputs

Figure 80. Equivalent Circuits of CW Summing Amplifier Inputs and Outputs

Figure 81. Equivalent Circuits of LVDS Outputs

8.3.8 LVDS Output Interface Description

The AFE5809 device has a LVDS output interface, which supports multiple output formats. The ADC resolutions can be configured as 12 bit or 14 bit as shown in the LVDS timing diagrams (Figure 1). The ADCs in the AFE5809 device are running at 14 bits; 2 LSBs are removed when 12-bit output is selected; and two zeros are added at LSBs when 16-bit output is selected. Appropriate ADC resolutions can be selected for optimizing system-performance cost effectiveness. When the devices run at 16-bit mode, higher-end FPGAs are required to process the higher rate of LVDS data. Corresponding register settings are listed in Table 4.

8.5.1 Serial Peripheral Interface (SPI) Operation

The AFE5809 device has two SPIs. The demodulator SPI interface is independent from the ADC/VCA SPI as shown in Figure 82. SPI_DIG_EN is used to select ADC/VCA SPI (SPI_DIG_EN='1') or demod SPI (SPI_DIG_EN='0').

Figure 82. SPI Interface in the AFE5809 Device

8.5.1.1 ADC/VCA Serial Register Write Description

Programming of different modes can be done through the serial interface formed by pins SEN (serial interface enable), SCLK (serial interface clock), SDATA (serial interface data), and RESET. All these pins have a pulldown resistor to GND of 20 kΩ. Serial shift of bits into the device is enabled when SEN is low. Serial data, SDATA, is latched at every rising edge of SCLK when SEN is active (low). The serial data is loaded into the register at every 24^th SCLK rising edge when SEN is low. If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiple of 24-bit words within a single active SEN pulse (an internal counter counts groups of 24 clocks after the falling edge of SEN). The interface can work with the SCLK frequency from 20 MHz to low speeds (of a few Hertz) and even with non-50% duty cycle SCLK. The data is divided into two main portions: a register address (8 bits) and the data itself (16 bits), to load on the addressed register. When writing to a register with unused bits, set these to 0. Figure 83 shows this process.

Figure 83. SPI Timing

NOTE

TI recommends synchronizing SCLK to ADC CLK. Typically, SCLK can be generated by dividing ADC CLK by an integer factor of N. In a system with multiple AFEs, SCLKs may not reach all AFEs simultaneously due to routing. To compensate routing differences and ensure AFEs’ outputs are aligned, SCLK can be adjusted to toggle on either the falling edge of ADCLK or the rising edge of ADC CLK (ensuring new register settings are loaded before next ADC sampling clock).

8.5.1.2 ADC/VCA Serial Register Readout Description

The device includes an option where the contents of the internal registers can be read back. This may be useful as a diagnostic test to verify the serial interface communication between the external controller and the AFE. First, the <REGISTER READOUT ENABLE> bit (Reg0[1]) needs to be set to 1. Then, the user should initiate a serial interface cycle specifying the address of the register (A7 through A0) whose content must be read. The data bits are don’t care. The device outputs the contents (D15 through D0) of the selected register on the SDOUT pin. SDOUT has a typical delay, t₈, of 20 ns from the falling edge of the SCLK. For lower speed SCLK, SDOUT can be latched on the rising edge of SCLK. For higher speed SCLK, for example, if the SCLK period is less than 60 ns, it is better to latch the SDOUT at the next falling edge of SCLK. Figure 84 shows this operation (the timing specifications follow the same information provided). In the readout mode, users still can access the <REGISTER READOUT ENABLE> through SDATA/SCLK/SEN. To enable serial register writes, set the <REGISTER READOUT ENABLE> bit back to 0.

The AFE5809 SDOUT buffer is tri-stated and gets enabled only when 0[1] (REGISTER READOUT ENABLE) is enabled. SDOUT pins from multiple AFE5809 devices can be tied together without any pullup resistors. Level shifter SN74AUP1T04 can be used to convert 1.8-V logic to 2.5-V/3.3-V logics if needed.

Figure 84. Serial Interface Register Read

8.6.1 ADC and VCA Register Description

A reset process is required at the AFE5809 device's initialization stage. Initialization can be done in one of two ways:

• Through a hardware reset, by applying a positive pulse in the RESET pin.
• Through a software reset, using the serial interface, by setting the SOFTWARE RESET bit to high. Setting this bit initializes the internal registers to the respective default values (all zeros), and then self-resets the SOFTWARE RESET bit to low. In this case, the RESET pin can stay low (inactive).

After reset, all ADC and VCA registers are set to 0, that is default setting. During register programming, all unlisted register bits must be set as 0.

Some demodulator registers are set as 1 after reset. During register programming, all unlisted register bits must be set as 0. In addition, the demodulator registers can be reset when 0x16[0] is set as 0. Thus, it is required to reconfigure the demodulator registers after toggling the 0x16[0] from 1 to 0.

8.6.1.2 AFE5809 ADC Register/Digital Processing Description

The ADC in the AFE5809 device has extensive digital processing functionality, which can be used to enhance ultrasound system performance. The digital processing blocks are arranged as in Figure 86.

Figure 86. ADC Digital Block Diagram

NOTE

These digital processing features are only available when the demodulation block is disabled. ADC output data directly enter the digital demodulator when the demod is enabled.

8.6.1.2.1 AVERAGING_ENABLE: Address: 2[11]

When set to 1, two samples, corresponding to two consecutive channels, are averaged (channel 1 with 2, 3 with 4, 5 with 6, and 7 with 8). If both channels receive the same input, the net effect is an improvement in SNR. The averaging is performed as:

• Channel 1 + channel 2 comes out on channel 3
• Channel 3 + channel 4 comes out on channel 4
• Channel 5 + channel 6 comes out on channel 5
• Channel 7 + channel 8 comes out on channel 6

8.6.1.2.2 ADC_OUTPUT_FORMAT: Address: 4[3]

The ADC output, by default, is in 2’s-complement mode. Programming the ADC_OUTPUT_FORMAT bit to 1 inverts the MSB, and the output becomes straight-offset binary mode.

NOTE

When the demodulation feature is enabled, only 2's complement format can be selected.

8.6.1.2.3 ADC Reference Mode: Address 1[13] and 3[15]

The following shows the register settings for the ADC internal reference mode and external reference mode.

• 0x1[13] 0x3[15] = 00: ADC internal reference mode, VREF_IN floating (pin M3)
• 0x1[13] 0x3[15] = 01: N/A
• 0x1[13] 0x3[15] = 10: N/A
• 0x1[13] 0x3[15] = 11: ADC external reference mode, VREF_IN = 1.4 V (pin M3)

8.6.1.2.4 DIGITAL_GAIN_ENABLE: Address: 3[12]

Setting this bit to 1 applies to each channel i the corresponding gain given by DIGTAL_GAIN_CHi <15:11>. The gain is given as 0 dB + 0.2 dB × DIGTAL_GAIN_CHi<15:11>. For instance, if DIGTAL_GAIN_CH5<15:11> = 3, channel 5 is increased by 0.6-dB gain. DIGTAL_GAIN_CHi <15:11> = 31 produces the same effect as DIGTAL_GAIN_CHi <15:11> = 30, setting the gain of channel i to 6 dB.

8.6.1.2.5 DIGITAL_HPF_ENABLE

• CH1 to CH4: Address 21[0]
• CH5 to CH8: Address 33[0]

8.6.1.2.6 DIGITAL_HPF_FILTER_K_CHX

• CH1 to CH4: Address 21[4:1]
• CH5 to CH8: Address 33[4:1]

This group of registers controls the characteristics of a digital high-pass transfer function applied to the output data, following Equation 4.

Equation 4.

These digital HPF registers (one for the first four channels and one for the second group of four channels) describe the setting of K. The digital HPF can be used to suppress low frequency noise, which commonly exists in ultrasound echo signals. The digital filter can significantly benefit near-field recovery time due to T/R switch low-frequency response. Table 3 shows the cut-off frequency versus K.

Table 3. Digital HPF –1-dB Corner Frequency versus K and Fs

k	40 MSPS	50 MSPS	65 MSPS
2	2780 kHz	3480 kHz	4520 kHz
3	1490 kHz	1860 kHz	2420 kHz
4	770 kHz	960 kHz	1250 kHz

8.6.1.2.7 LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]

The low-frequency noise suppression mode is especially useful in applications where good noise performance is desired in the frequency band of 0 to 1 MHz (around DC). Setting this mode shifts the low-frequency noise of the AFE5809 device to approximately Fs / 2, thereby moving the noise floor around DC to a much lower value. Register bit 1[11] is used for enabling or disabling this feature. When this feature is enabled, power consumption of the device is increased slightly by approximately 1 mW/CH.

8.6.1.2.8 LVDS_OUTPUT_RATE_2X: Address: 1[14]

The output data always uses a DDR format, with valid/different bits on the positive as well as the negative edges of the LVDS bit clock, DCLK. The output rate is set by default to 1× (LVDS_OUTPUT_RATE_2X = 0), where each ADC has one LVDS stream associated with it. If the sampling rate is low enough, two ADCs can share one LVDS stream, in this way lowering the power consumption devoted to the interface. The unused outputs will output zero. To avoid consumption from those outputs, no termination should be connected to them. The distribution on the used output pairs is done in the following way:

• Channel 1 and channel 2 come out on channel 3. Channel 1 comes out first.
• Channel 3 and channel 4 come out on channel 4. Channel 3 comes out first.
• Channel 5 and channel 6 come out on channel 5. Channel 5 comes out first.
• Channel 7 and channel 8 come out on channel 6. Channel 7 comes out first.

8.6.1.2.9 CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]

Setting this bit to 1 enables the subtraction of the value on the corresponding OFFSET_CHx<9:0> (offset for channel i) from the ADC output. The number is specified in 2's complement format. For example, OFFSET_CHx<9:0> = 11 1000 0000 means subtract –128. For OFFSET_CHx<9:0> = 00 0111 1111 the effect is to subtract 127. In effect, both addition and subtraction can be performed. The offset is applied before the digital gain (see DIGITAL_GAIN_ENABLE). The whole data path is 2's complement throughout internally, with digital gain being the last step. Only when ADC_OUTPUT_FORMAT = 1 (straight binary output format) is the 2's complement word translated into offset binary at the end.

8.6.1.2.10 SERIALIZED_DATA_RATE: Address: 3[14:13]

See Table 4 for detailed description.

Table 4. Corresponding Register Settings

LVDS Rate	12 bit (6× DCLK)	14 bit (7× DCLK)	16 bit (8× DCLK)
Register 3 [14:13]	11	00	01
Register 4 [2:0]	010	000	000
Description	2 LSBs removed	N/A	2 zeroes added at LSBs

8.6.1.2.11 TEST_PATTERN_MODES: Address: 2[15:13]

The AFE5809 device can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal ADC data output. The device may also be made to output 6 preset patterns:

• Ramp: Setting Register 2[15:13] = 111 causes all the channels to output a repeating full-scale ramp pattern. The ramp increments from zero code to full-scale code in steps of 1 LSB every clock cycle. After hitting the full-scale code, it returns back to zero code and ramps again.
• Zeros: The device can be programmed to output all 0 s by setting Register 2[15:13] = 110.
• Ones: The device can be programmed to output all 1 s by setting Register 2[15:13] = 100.
• Deskew Patten: When 2[15:13] = 010; this mode replaces the 14-bit ADC output with the 01010101010101 word.
• Sync Pattern: When 2[15:13] = 001, the normal ADC output is replaced by a fixed 11111110000000 word.
• Toggle: When 2[15:13] = 101, the normal ADC output is alternating from 1 s to 0 s. The start state of ADC word can be either 1 s or 0 s.
• Custom Pattern: It can be enabled when 2[15:13] = 011. Users can write the required VALUE into register bits <CUSTOM PATTERN>, which is Register 5[13:0]. Then, the device will output VALUE at its outputs, about 3 to 4 ADC clock cycles after the 24^th rising edge of SCLK. So, the time taken to write one value is 24 SCLK clock cycles + 4 ADC clock cycles. To change the customer pattern value, users can repeat writing Register 5[13:0] with a new value. Due to the speed limit of SPI, the refresh rate of the custom pattern may not be high. For example, 128 points custom pattern takes approximately 128 × (24 SCLK clock cycles + 4 ADC clock cycles).

NOTE

Only one of the above patterns can be active at any given instant. Test pattern from the ADC output stage can NOT be sent to the demodulator; it can only be sent to the LVDS serializer when the demodulator is off.

8.6.1.2.12 SYNC_PATTERN: Address: 10[8]

By enabling this bit, all channels' test pattern outputs are synchronized. When 10[8] is set as 1, the ramp patterns of all 8 channels start simultaneously.

8.6.2 Digital Demodulator Register Description

spacer

1. LVDS Serializer configuration:
   • Serialization Factor 0x03[14:13]: It can be set using demodulator register SERZ_FACTOR. Default serialization factor for the demodulator is 16×. However, the actual LVDS clock speed can be set by the serialization factor in the ADC SPI interface as well; the ADC serialization factor is adjusted to 14× by default. Therefore, it is necessary to sync these two settings when the demodulator is enabled, that is, set the ADC register 0x03[14:13] = 01. For RF mode (passing 14 bits only), demodulator serialization factor can be changed to 14× by setting demodulator register 0xC3[14:13] to 10.
   • Output Resolution 0x03[11:9]: In the default setting, it is 14 bits. The demodulator output resolution depends on the decimation factor. 16-bit resolution can be used when higher decimation factor is selected.
2. Channel selection:
   • Using register MODULATE_BYPASS 0x0A[14], channel output mode can be selected as IQ modulated or single-channel I or Q output.
   • Channel output is also selected using registers OUTPUT_CHANNEL_SEL 0x0A[11] and FULL_LVDS_MODE 0x0A[9] and decimation factor.
   • Each of the two demodulator subchips in a device has four channels named A, B, C, and D.

NOTE

After decimation, the LVDS FCLK rate keeps the same as the ADC sampling rate. Considering the reduced data amount, zeros are appended after I and Q data and ensure the LVDS data rate matches the LVDS clock rate. For detailed information about channel multiplexing, see Table 13. In the table, A.I refers to CHA in-phase output, and A.Q refers to CHA quadrature output. For example, M = 3, the valid data output rate is Fs / 3 for both I and Q channels, that is 2 × Fs / 3 bandwidth is occupied. The left Fs / 3 bandwidth is then filled by M-2 zeros. As a result, the demod LVDS output data are A.I, A.Q, 0, A.I A.Q 0 after SYNC_WORD, FCLK = Fs and DCLK = Fs × 8. When two ADC CHs' data are transferred by one LVDS lane, M-4 zeros are filled after A.I, A.Q, B.I, and B.Q. See more details in Table 13 and Figure 87.

Table 13. Channel Selection⁽¹⁾

Decimation Factor (M)	Modulate Bypass	Output Channel Select	Full LVDS Mode	Decimation Factor M	LVDS Output Description
M ≥ 2	0	0	0	M < 4	LVDS1: A.I, A.Q, (zeros)
					LVDS2: B.I, B.Q, (zeros)
					LVDS3: C.I, C.Q, (zeros)
					LVDS4: D.I, D.Q, (zeros)
				M ≥ 4	LVDS1: A.I, A.Q, B.I, B.Q, (zeros) LVDS2: idle
					LVDS3: C.I, C.Q, D.I, D.Q, (zeros) LVDS4: idle
			1	X	LVDS1: A.I, A.Q, (zeros)
					LVDS2: B.I, B.Q, (zeros)
					LVDS3: C.I, C.Q, (zeros)
					LVDS4: D.I, D.Q, (zeros)
		1	0	M < 4	LVDS1: B.I, B.Q, (zeros)
					LVDS2: A.I, A.Q, (zeros)
					LVDS3: D.I, D.Q, (zeros)
					LVDS4: C.I, C.Q, (zeros)
				M ≥ 4	LVDS1: B.I, B.Q, A.I, A.Q, (zeros)
					LVDS2: idle
					LVDS3: D.I, D.Q, C.I, C.Q, (zeros)
					LVDS4: idle
			1	X	LVDS1: B.I, B.Q, (zeros)
					LVDS2: A.I, A.Q, (zeros)
					LVDS3: D.I, D.Q, (zeros)
					LVDS4: C.I, C.Q, (zeros)
M ≥ 2	1	0	X	X	LVDS1: A.I; Note: the same A.I is repeated by M times.
					LVDS2: A.Q; Note: the same A.Q is repeated by M times.
					LVDS3: C.I; Note: the same C.I is repeated by M times.
					LVDS4: C.Q; Note: the same C.Q is repeated by M times.
		1	X	X	LVDS1: B.I; Note: the same B.I is repeated by M times.
					LVDS2: B.Q; Note: the same B.Q is repeated by M times.
					LVDS3: D.I; Note: the same D.I is repeated by M times.
					LVDS4: D.Q; Note: the same D.Q is repeated by M times.
M = 1	0	0	X	1	LVDS1: A.I; LVDS2: B.I; LVDS3: C.I; LVDS4: D.I
M = 1	0	1	X	1	LVDS1: B.I; LVDS2: A.I; LVDS3: D.I; LVDS4: C.I
M = 1	1	0	X	1	LVDS1: A.I; LVDS2: A.Q; LVDS3: C.I; LVDS4: C.Q
M = 1	1	1	X	1	LVDS1: B.I; LVDS2: B.Q; LVDS3: D.I; LVDS4: D.Q

(1) This table refers to individual demodulator subchip, which has four LVDS outputs, that is LVDS1 through LVDS4; and four input CHs, that is CH.A to CH.D. See Figure 85.
Figure 87. Output Data Format at M = 3~5
3. Output mode:
   • Using register OUT_MODE, ramp pattern and custom pattern can be enabled.
   • Custom pattern: In the case of a custom pattern, custom pattern value can be set using register CUSTOM_PATTERN. Note: LSB always comes out first regardless of whether 0x04[4] = 0 or 1, that is, MSB_FIRST = 0 or 1.
   • Ramp pattern: Demodulator generated ramp pattern includes information of chip_id as well. 8 MSB (that is, Data[15..8]) bits are ramp pattern. Next 5 bits (that is, Data[3..7]) gives value of chip ID. Data[2] corresponds to subchip ID, 0 or 1; Data[1:0] are filled with zeros.

NOTE

Test pattern from the ADC output stage can NOT be sent to the demodulator; it can only be sent to the LVDS serializer when the demodulator is off.

8.6.2.1.3 Programming the Coefficient RAM

1. Set SPI address 0xC6[7:0] with the base address, for example 0x0000. 0xC6 means both demodulator subchips are enabled.
2. Write 112 bits to SPI address 0xC7 (MSB first). Each coefficient memory word consists of eight 14-bit coefficients, which are aligned in the following manner: coefficient order from right to left and bit order from right to left.

NOTE

The coefficients are in 2s complement format.

Figure 90.

Coeff 7[13:0]	Coeff 6[13:0]	Coeff 5[13:0]	Coeff 4[13:0]	Coeff 3[13:0]	Coeff 2[13:0]	Coeff 1[13:0]	Coeff 0[13:0]
111:98	97:84	83:70	69:56	55:42	41:28	27:14	13:0

NOTE

SPI serialization is done from left to right (Coeff 7[13] first and Coeff 0[0] last).

3. Repeat the previous step for the following coefficient bulk entries (the address in register 0xC6 auto increments).

8.6.2.1.4 Filter Coefficent Test Mode

Coefficient test mode allows for the streaming of coefficients through the demodulator to the LVDS. Filter coefficient test mode can be set by the following:

1. Enable TM_COEFF_EN.
2. Write OUTPUT_RESOLUTION (0x03[11:9]) = 0b100, that is, 16-bit output. (output bit resolution of 14 bits will not give proper result.)
3. Write DC_REMOVAL_BYPASS (0x0A[0]) = 1, DWN_CNV_BYPASS (0x0A[2]) = 1.
4. Write DC_DEC_SHIFT_FORCE_EN (0x1D[7]) = 1, DEC_SHIFT_FORCE (0x1D[6:4] = 0b110, and DEC_SHIFT_SCALE (0x0a[13]) = 1.
5. Write MODULATE_BYPASS (0x0A[14]) = 1. After writing all of the above settings, coefficients come at the output in the sequence as follow.
6. M = 2
   • Address 0: C15 C13 C11 C09 C07 C05 C03 C01; Address 1: C14 C12 C10 C08 C06 C04 C02 C00
   • The order in which coefficients come at the output will be: 0 C01 C03 C05 C07 C09 C11 C13 C15 C14 C12 C10 C08 C06 C04 C02 C00 C00 C02 C04 C06 C08 C10 C12 C14 C15 C13 C11 C09 C07 C05 C03 C01 0
7. M = 8
   • The coefficients come to the output as shown in Figure 91.

NOTE:

When it reaches the last sample, it starts giving coefficients in the reverse direction until it reaches the point it started.

Figure 91. Coefficient Readout Sequence

8.6.2.1.5 TX_SYNC and SYNC_WORD Timing

As shown in Figure 92, hardware TX_SYNC is latched at the next negative edge of the ADC Clock after 0 to 1 transition of TX_SYNC. The time gap between latched edge and the start of the LVDS SYNC_WORD is kT ns where T is the time period of ADC clock and k = 16 + decFactor + 1. t_SETUP and t_HOLD can be considered as 1.5 ns in the normal condition. Both are at the negative edge of the ADC clock.

Figure 92. Sync Word Generation With Respect to TX_TRIG when DC_REMOVAL_BYPASS 10[0] = 0

8.6.2.1.6 FIR Filter Delay versus TX_TRIG Timing

The AFE5809 device’s decimation filter is a symmetric M×16-order FIR filter, where M is the decimation factor from 1 to 32. Half of the M×16 coefficients are stored in the filter coefficient memory.

For a discrete-time FIR filter, its output is a weighted sum of the current and a finite number of previous values of the input as Equation 7 shows.

Equation 7.

where

• X[n] is the input signal.
• Y[n] is the output signal.
• CN is the filter coefficients.
• N is the filter order.

Therefore, the delay of the AFE5809 output is related to decimation factor, M. The TX_TRIG timing also plays a role in this. In the following description, M = 1 and M = 2 are used as examples to derive a generic timing relationship among TX_TRIG, AFE input, and AFE output.

The following register settings were used when the delay relationship was measured:

Table 23. Settings for evaluating FIR Filter Delay versus TX_TRIG Timing

Register Setting	Register Setting (HEX)	Description
22[0] = 1	0x16[0] = 1	Enable demodulator. 0x16 belongs to ADC register
Profile RAM	Profile RAM	Set different decimation factor and other settings in profile RAM.
Coeff RAM	Coeff RAM	Write filter coefficients in coefficient memory.
29[7] = 1	0x1D[7] = 1	Set DEC_SHIFT_FORCE_EN
10[13] = 1	0xA[13] = 1	Set DEC_SHIFT_SCALE
29[6:4] = 6	0x1D[6:4] = 6	Set DEC_SHIFT_FORCE
10[15] = 0, 10[12] = 1, 10[4] = 1, 10[1] = 1;	0xA[15] = 0, 0xA[12] = 1, 0xA[4] = 1, 0xA[1] = 1	RESERVED bits
10[0] = 1	0x0A[0] = 1	Set DC_REMOVAL_BYPASS
10[10] = 1	0x0A[10] = 1	Reset down conversion phase on TX_TRIG
03[14:13] = 11	03[14:13] = 11	SERZ_FACTOR 16X
03[11:9] = 100	03[11:9] = 100	OUTPUT_RESOLUTION 16X
04[4] = 1	04[4] = 1	MSB_FIRST
11[15:0]	0xB[15:0]	Set custom SYNC_WORD value if needed
10[2]=0	0x0A[2]=0	Down conversion is enabled.
Profile RAM[21:6]=0	Profile RAM[21:6]=0	Down convert frequency set to 0, that is, multiply input signal with DC.
Note: Even if this frequency is set to a non-zero value, it will not change the demod latency. For experiment ease, mixing with DC is performed. ADC sampling frequency and VCA LPF settings were kept such that the AFE5809’s demod sees a single pulse.

When M = 1, 8 filter coefficients written in the memory are C0, C1 to C7. An impulse signal is applied at both VCA input and TX_TRIG. Due to the impulse input, coefficients start coming at the output according to timing diagram shown in Figure 93, where 20-cycle delay is observed.

Figure 93. Expected Latency Timing When M = 1

By adjusting the timing between AFE input and TX_TRIG, the user can obtain a timing diagram similar to Figure 93.

Figure 94. Measured Latency Timing When M = 1

By adjusting the timing between AFE input and TX_TRIG, the user can obtain a timing diagram similar to Figure 94.

When M = 2, if the impulse is given one clock before TX_TRIG signal, then the demod output after sync word gives impulse response of the filter as shown in Figure 95.

Figure 95. Measured Latency Timing When M = 2

Figure 96 shows a generic timing diagram. The number of zeros comes before the sync word is equal to Z. The sync word comes after S number of cycles, impulse response starts coming after L number of cycles, and input impulse is given after IP cycles with respect to TX_TRIG signal. Therefore, for different decimation factor (M), values of these numbers are listed in Table 24 and Figure 96.

Table 24. Generic Latency versus Decimation Factor M⁽²⁾⁽³⁾

M	Number of Zeros (ZNo)	Sync Word Latency (S)	Data Latency (L)	Input Impulse (IP)(1)
1	2	17	18	–2
2	3	18	19	–1
3	4	19	20	0
4	5	20	21	1
5	6	21	22	2
6	7	22	23	3
7	8	23	24	4
8	9	24	25	5
M	M + 1	16 + M	17 + M	M – 3

(1) Negative number represents input is given in advance with respect to TX_TRIG signal.

(2) When DC_REMOVAL_BYPASS 10[0] = 0 or 0xA[0] = 0, the sync word latency and data latency becomes 17 + M and 18 + M

(3) ADC's low latency mode enabled by register 0x2[12] does not impact S and L.

Figure 96. Measured Latency Timing at Any M

8.6.2.1.6.0.1 Expression of Decimation Filter Response

Based on Table 24, the decimation filter’s response is formulated. Figure 97 indicates that the Tx_Trig sample is considered as the reference for time scale. So, the input to the device at Tx_Trig clock will be expressed as X[0], the next sample input as X[1], and so on. Similarly, the output of the device followed by the AFE5809’s demodulator will be expressed as Y[0] at the instant of Tx_Trig, Y[1] at the next clock, and so on; Cn or C(n) indicates the coefficient of n^th index.

Figure 97. Typical Timing Expression Among ADC CLK, Input, TX_TRIG, and Output

For M = 1, the number of zeros, ZNo = 2; Sync word latency S = 17. So, the output values from sample 18 are relevant and the first few samples are:

Y[18] = C0×X[-2]+C1×X[-3]+C2×X[-4]+…+C7×X[-9]+C7×X[-10]+…+C[0]×X[-17]

Y[19] = C0×X[-1]+C1×X[-2]+C2×X[-3]+…+C7×X[-8]+C7×X[-9]+…+C[0]×X[-16]

Y[20] = C0×X[0]+C1×X[-1]+C2×X[-2]+…+C7×X[-7]+C7×X[-8]+…+C[0]×X[-15]

Equation 8.

All these samples appear at the output because no samples are dropped for decimation factor = 1.

For M = 2, the number of zeros, ZNo = 3; Sync word latency S = 18. So, the output values from sample 19 are relevant and the first few samples are described as:

Y[19] = C0×X[-1]+C1×X[-2]+C2×X[-3]+…+C15×X[-16]+C15×X[-17]+…+C[0]×X[-32]

Y[20] = C0×X[0]+C1×X[-1]+C2×X[-2]+…+C15×X[-15]+C15×X[-16]+…+C[0]×X[-31]

Y[21] = C0×X[1]+C1×X[0]+C2×X[-1]+…+C15×X[-14]+C15×X[-15]+…+C[0]×X[-30]

Equation 9.

But for M = 2, every alternate sample must be dropped. The decimation is adjusted in such a way that the first sample after sync is retained. Hence in this case, Y[19], Y[21], Y[23], and so forth are retained and Y[20], Y[22], Y[24], and so forth are dropped.

For M = 3, the number of zeros, ZNo = 4; Sync word latency S = 19. So, the output values from sample 20 are relevant and the first few samples are described as:

Y[20] = C0×X[0]+C1×X[-1]+C2×X[-2]+…+C23×X[-23]+C23×X[-24]+…+C[0]×X[-47]

Y[21] = C0×X[1]+C1×X[0]+C2×X[-1]+…+C23×X[-22]+C23×X[-23]+…+C[0]×X[-46]

Y[22] = C0×X[2]+C1×X[1]+C2×X[0]+…+C23×X[-21]+C23×X[-22]+…+C[0]×X[-45]

Y[23] = C0×X[3]+C1×X[2]+C2×X[1]+…+C23×X[-20]+C23×X[-21]+…+C[0]×X[-44]

Equation 10.

But for M = 3, the last two of every three samples must be dropped. The decimation is adjusted in such a way that the first sample after sync is retained. Hence in this case, Y[20], Y[23], Y[26], and so forth are retained and Y[21], Y[22], Y[24], Y[25], and so forth are dropped.

For any M, this pattern can be generalized for a decimation factor of M. The number of ZNo = M + 1, Sync word latency S = 16 + M. So, the output values from sample (17 + M) are relevant and the first few samples are described as:

Y[17+M] = C0×X[M-3]+C1×X[M-4]+C2×X[M-5]+…+C(8M-1)×X[-7M-2]+C(8M-1)×X[-7M-3]+ … +C[0]×X[-15M-2]

Y[18+M] = C0×X[M-2]+C1×X[M-3]+C2×X[M-4]+…+C(8M-1)×X[-7M-1]+C(8M-1)×X[-7M-2]+ … +C[0]×X[-15M-1]

Equation 11.

For a decimation factor of M which is not 1, the decimation is adjusted in such a way that the first sample after sync is retained. Hence in this case, Y[17 + M], Y[17 + 2M], Y[17 + 3M], and so forth are retained and the rest of samples between these, that is, Y[18 + M], Y[19 + 2M],…, Y[16 + 2M] are dropped.