SLOS738E September   2012  – August 2015 AFE5809

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Digital Demodulator Electrical Characteristics
    7. 7.7  Digital Characteristics
    8. 7.8  Switching Characteristics
    9. 7.9  SPI Switching Characteristics
    10. 7.10 Output Interface Timing Requirements (14-bit)
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 LNA
      2. 8.3.2 Voltage-Controlled Attenuator
      3. 8.3.3 PGA
      4. 8.3.4 ADC
      5. 8.3.5 Continuous-Wave (CW) Beamformer
        1. 8.3.5.1 16 × ƒcw Mode
        2. 8.3.5.2 8 × ƒcw and 4 × ƒcw Modes
        3. 8.3.5.3 1 × ƒcw Mode
      6. 8.3.6 Digital I/Q Demodulator
      7. 8.3.7 Equivalent Circuits
      8. 8.3.8 LVDS Output Interface Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Operation
        1. 8.5.1.1 ADC/VCA Serial Register Write Description
        2. 8.5.1.2 ADC/VCA Serial Register Readout Description
        3. 8.5.1.3 Digital Demodulator SPI Description
    6. 8.6 Register Maps
      1. 8.6.1 ADC and VCA Register Description
        1. 8.6.1.1 ADC Register Map
        2. 8.6.1.2 AFE5809 ADC Register/Digital Processing Description
          1. 8.6.1.2.1  AVERAGING_ENABLE: Address: 2[11]
          2. 8.6.1.2.2  ADC_OUTPUT_FORMAT: Address: 4[3]
          3. 8.6.1.2.3  ADC Reference Mode: Address 1[13] and 3[15]
          4. 8.6.1.2.4  DIGITAL_GAIN_ENABLE: Address: 3[12]
          5. 8.6.1.2.5  DIGITAL_HPF_ENABLE
          6. 8.6.1.2.6  DIGITAL_HPF_FILTER_K_CHX
          7. 8.6.1.2.7  LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11]
          8. 8.6.1.2.8  LVDS_OUTPUT_RATE_2X: Address: 1[14]
          9. 8.6.1.2.9  CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8]
          10. 8.6.1.2.10 SERIALIZED_DATA_RATE: Address: 3[14:13]
          11. 8.6.1.2.11 TEST_PATTERN_MODES: Address: 2[15:13]
          12. 8.6.1.2.12 SYNC_PATTERN: Address: 10[8]
        3. 8.6.1.3 VCA Register Map
        4. 8.6.1.4 VCA Register Description
          1. 8.6.1.4.1 LNA Input Impedances Configuration (Active Termination Programmability)
          2. 8.6.1.4.2 Programmable Gain for CW Summing Amplifier
          3. 8.6.1.4.3 Programmable Phase Delay for CW Mixer
      2. 8.6.2 Digital Demodulator Register Description
        1. 8.6.2.1 Profile RAM and Coefficient RAM
          1. 8.6.2.1.1 Programming the Profile RAM
          2. 8.6.2.1.2 Procedure for Configuring Next Profile Vector
          3. 8.6.2.1.3 Programming the Coefficient RAM
          4. 8.6.2.1.4 Filter Coefficent Test Mode
          5. 8.6.2.1.5 TX_SYNC and SYNC_WORD Timing
          6. 8.6.2.1.6 FIR Filter Delay versus TX_TRIG Timing
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 LNA Configuration
          1. 9.2.2.1.1 LNA Input Coupling and Decoupling
          2. 9.2.2.1.2 LNA Noise Contribution
          3. 9.2.2.1.3 Active Termination
          4. 9.2.2.1.4 LNA Gain Switch Response
        2. 9.2.2.2 Voltage-Controlled Attenuator
        3. 9.2.2.3 CW Operation
          1. 9.2.2.3.1 CW Summing Amplifier
          2. 9.2.2.3.2 CW Clock Selection
          3. 9.2.2.3.3 CW Supporting Circuits
        4. 9.2.2.4 Low Frequency Support
        5. 9.2.2.5 ADC Operation
          1. 9.2.2.5.1 ADC Clock Configurations
          2. 9.2.2.5.2 ADC Reference Circuit
      3. 9.2.3 Application Curves
    3. 9.3 System Example
      1. 9.3.1 ADC Debug
      2. 9.3.2 VCA Debug
    4. 9.4 Do's and Don'ts
      1. 9.4.1 Driving the Inputs (Analog or Digital) Beyond the Power-Supply Rails
      2. 9.4.2 Driving the Device Signal Input With an Excessively High Level Signal
      3. 9.4.3 Driving the VCNTL Signal With an Excessive Noise Source
      4. 9.4.4 Using a Clock Source With Excessive Jitter, an Excessively Long Input Clock Signal Trace, or Having Other Signals Coupled to the ADC or CW Clock Signal Trace
      5. 9.4.5 LVDS Routing Length Mismatch
      6. 9.4.6 Failure to Provide Adequate Heat Removal
  10. 10Power Supply Recommendations
    1. 10.1 Power/Performance Optimization
    2. 10.2 Power Management Priority
    3. 10.3 Partial Power-Up and Power-Down Mode
    4. 10.4 Complete Power-Down Mode
    5. 10.5 Power Saving in CW Mode
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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订购信息

6 Pin Configuration and Functions

ZCF Package
135-Pin NFBGA
Bottom View
AFE5809 po_bottom_bw_bos73.gif

Pin Functions

PIN DESCRIPTION
NAME NO.
ACT1 to ACT8 B9 to B2 Active termination input pins for CH1 to CH8
AVDD A1 3.3-V analog supply for LNA, VCAT, PGA, LPF, and CWD blocks
D8
D9
E8
E9
K1
AVDD_5V K2 5-V analog supply for LNA, VCAT, PGA, LPF, and CWD blocks
AVDD_ADC J6 1.8-V analog power supply for ADC
J7
K8
L3
M1
M2
AVSS C1 Analog ground
D1 to D7
E3 to E7
F3 to F7
G1 to G7
H3 to H7
J3 to J5
K6
CLKM_ADC L2 Negative input of differential ADC clock. In the single-end clock mode, it can be tied to GND directly or through a 0.1-µF capacitor.
CLKP_ADC L1 Positive input of differential ADC clock. In the single-end clock mode, it can be tied to clock signal directly or through a 0.1-µF capacitor.
CLKM_16X F9 Negative input of differential CW 16× clock. Tie to GND when the CMOS clock mode is enabled. In the 4× and 8× CW clock modes, this pin becomes the 4× or 8× CLKM input. In the 1× CW clock mode, this pin becomes the in-phase 1× CLKM for the CW mixer. Can be floated if CW mode is not used. See register 0x36[11:10].
CLKP_16X F8 Positive input of differential CW 16× clock. In 4× and 8× clock modes, this pin becomes the 4× and 8× CLKP input. In the 1× CW clock mode, this pin becomes the in-phase 1× CLKP for the CW mixer. Can be floated if CW mode is not used.See register 0x36[11:10].
CLKM_1X G9 Negative input of differential CW 1× clock. Tie to GND when the CMOS clock mode is enabled (refer to Figure 107 for details). In the 1× clock mode, this pin is the quadrature-phase 1× CLKM for the CW mixer. Can be floated if CW mode is not used.
CLKP_1X G8 Positive input of differential CW 1× clock. In the 1× clock mode, this pin is the quadrature-phase 1× CLKP for the CW mixer. Can be floated if CW mode is not used.
CM_BYP B1 Bias voltage and bypass to ground. TI recommends 1 µF. To suppress the ultra-low frequency noise, the designer can use 10 µF.
CW_IP_AMPINM E2 Negative differential input of the in-phase summing amplifier. External LPF capacitor must be connected between CW_IP_AMPINM and CW_IP_OUTP. This pin provides the current output for the CW mixer. This pin becomes the CH7 PGA negative output when PGA test mode is enabled. Can be floated if not used.
CW_IP_AMPINP E1 Positive differential input of the in-phase summing amplifier. External LPF capacitor must be connected between CW_IP_AMPINP and CW_IP_OUTM. This pin provides the current output for the CW mixer. This pin becomes the CH7 PGA positive output when PGA test mode is enabled. Can be floated if not used.
CW_IP_OUTM F1 Negative differential output for the in-phase summing amplifier. External LPF capacitor must be connected between CW_IP_AMPINP and CW_IP_OUTPM. Can be floated if not used.
CW_IP_OUTP F2 Positive differential output for the in-phase summing amplifier. External LPF capacitor must be connected between CW_IP_AMPINM and CW_IP_OUTP. Can be floated if not used.
CW_QP_AMPINM J2 Negative differential input of the quadrature-phase summing amplifier. External LPF capacitor must be connected between CW_QP_AMPINM and CW_QP_OUTP. This pin provides the current output for the CW mixer. This pin becomes CH8 PGA negative output when PGA test mode is enabled. Can be floated if not used.
CW_QP_AMPINP J1 Positive differential input of the quadrature-phase summing amplifier. External LPF capacitor must be connected between CW_QP_AMPINP and CW_QP_OUTM. This pin provides the current output for the CW mixer. This pin becomes CH8 PGA positive output when PGA test mode is enabled. Can be floated if not used.
CW_QP_OUTM H1 Negative differential output for the quadrature-phase summing amplifier. External LPF capacitor must be connected between CW_QP_AMPINP and CW_QP_OUTM. Can be floated if not used.
CW_QP_OUTP H2 Positive differential output for the quadrature-phase summing amplifier. External LPF capacitor must be connected between CW_QP_AMPINM and CW_QP_OUTP. Can be floated if not used.
D1M to D8M N8 ADC CH1 to CH8 LVDS negative outputs
P9 to P7
P3 to P1
N2
D1P to D8P N9 ADC CH1 to 8 LVDS positive outputs
R9 to R7
R3 to R1
N1
DCLKM P6 LVDS bit clock (7x) negative output
DCLKP R6 LVDS bit clock (7x) positive output
DVDD N3 ADC digital and I/O power supply, 1.8 V
N7
DVSS N5 ADC digital ground
P5
R5
DVDD_LDO1, DVDD_LDO2 N4 When LDO_EN L4 = 1.8 V, demodulator digital power supply generated internally. These two pins should be separated on the PCB and decoupled respectively with 0.1-µF capacitors. When LDO_EN L4=DVSS, the internal LDOs are disabled. External higher performance 1.4-V supply can be applied to N4 and N6 for minimizing digital noise emission.
N6
FCLKM P4 LVDS frame clock (1×) negative output
FCLKP R4 LVDS frame clock (1×) positive output
INM1 to INM8 C9 to C2 CH1 to CH8 complementary analog inputs. Bypass to ground with ≥0.015-µF capacitors. The HPF response of the LNA depends on the capacitors.
INP1 to INP8 A9 to A2 CH1 to CH8 analog inputs. AC couple to inputs with ≥0.1-µF capacitors.
LDO_EN L6 Enable/Disable AFE's internal LDO regulators. When it is tied to 1.8-V DVDD or Logic "1", AFE's internal LDO is enabled. When it is tied to DVSS or Logic "0", AFE's internal LDO is disabled and external 1.4-V supply can be applied at N4 and N6 pins, that is, DVDD_LDO1, DVDD_LDO2.
LDO_SETV M6 Sets the internal LDO votlage. Logic "1" or tie to 1.8-V DVDD sets the LDO output as 1.4V. It can be tied to DVSS when the internal LDO is disabled.
PDN_ADC L8 ADC partial (fast) power-down control pin with an internal pulldown resistor of 100 kΩ. Active high. Either 1.8-V or 3.3-V logic level can be used.
PDN_VCA J8 VCA partial (fast) power-down control pin with an internal pulldown resistor of 20 kΩ. Active high. 3.3-V logic level should be used.
PDN_GLOBAL H8 Global (complete) power-down control pin for the entire chip with an internal pulldown resistor of 20 kΩ. Active high. 3.3-V logic level should be used. When the complete power-down mode is enabled, the digital demodulator may lose register settings. Therefore, it is required to reconfigure the demodulator registers, filter coefficient memory, and profile memory after existing the complete power-down mode.
REFM L4 0.5-V reference output in the internal reference mode. Must leave floated in the internal reference mode. TI recommends adding a test point on the PCB for monitoring the reference output
REFP M4 1.5-V reference output in the internal reference mode. Must leave floated in the internal reference mode. TI recommends adding a test point on the PCB for monitoring the reference output
RESET H9 Hardware reset pin with an internal pulldown resistor of 20 kΩ. Active high. The designer can use 3.3-V logic level.
SCLK J9 Serial interface clock input with an internal pulldown resistor of 20 kΩ. This pin is connected to both ADC and VCA. The designer should use 3.3-V logic.
SDATA K9 Serial interface data input with an internal pulldown resistor of 20 kΩ. This pin is connected to both ADC and VCA. The designer should use 3.3-V logic.
SDOUT M9 Serial interface data readout. High impedance when readout is disabled. This pin is connected to ADC only. The designer can use 1.8-V logic.
SEN L9 Serial interface enable with an internal pullup resistor of 20 kΩ. Active low. This pin is connected to both ADC and VCA. The designer should use 3.3-V logic.
SPI_DIG_EN M7 Serial interface enable for the digital demodulator memory space. SPI_DIG_EN pin is required to be set to 0 during SPI transactions to demodulator registers. Each transaction starts by setting SEN as 0 and terminates by setting it back to 1 (similar to other register transactions). Pull up internally through a 20-kΩ resistor. This pin is connected to both ADC and VCA. The designer should use 3.3-V logic.
TX_SYNC_IN L7 System trig signal input. It indicates the start of signal transmission. Either 3.3-V or 1.8-V logic level can be used. Note: TX_SYNC signal must be synchronized with ADC CLK. Typically, pulse repetition frequency (PRF) signal can be used for TX_SYNC_IN.
VCNTLM K4 Negative differential attenuation control pin
VCNTLP K3 Positive differential attenuation control pin
VHIGH K5 Bias voltage; bypass to ground with ≥1 µF
VREF_IN M3 ADC 1.4-V reference input in the external reference mode; bypass to ground with 0.1 µF.
DNC K7 Do not connect. Must leave floated
L5
M5
M8
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