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SLOS738E September 2012 – August 2015 AFE5809

PRODUCTION DATA.

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ZCF|135
- MPBG840

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage	AVDD	–0.3	3.9	V
	AVDD_ADC	–0.3	2.2
	AVDD_5V	–0.3	6
	DVDD	–0.3	2.2
	DVDD_LDO	–0.3	1.6
Voltage between AVSS and LVSS		–0.3	0.3	V
Voltage at analog inputs and digital inputs		–0.3	min [3.6, AVDD + 0.3]	V
Peak solder temperature⁽²⁾			260	°C
Maximum junction temperature (T_J), any condition			105	°C
Operating temperature		0	85	°C
Storage temperature, T_stg		–55	150	°C

(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.

(2) Device complies with JSTD-020D.

7.2 ESD Ratings

			VALUE		UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±1000		V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±250		V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

	MIN	MAX	UNIT
AVDD	3.15	3.6	V
AVDD_ADC	1.7	1.9	V
DVDD	1.7	1.9	V
DVDD_LDO1/2 (internally generated)	1.2	1.4	V
DVDD_LDO1/2 (external supplied)	1.4	1.5	V
AVDD_5V	4.75	5.5	V
Ambient temperature, T_A	0	85	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		AFE5809	UNIT
		BGA (NFBGA)
		135 PINS
R_θJA	Junction-to-ambient thermal resistance	34.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	5	°C/W
R_θJB	Junction-to-board thermal resistance	11.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
ψ_JB	Junction-to-board characterization parameter	10.8	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1 µF at INP and bypassed to ground with 15 nF at INM, No active termination, V_CNTL = 0 V, ƒ_IN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65 MSPS, LPF Filter = 15 MHz, low-noise mode, V_OUT = –1 dBFS, Single-ended V_CNTL mode, VCNTLM = GND, ADC configured in internal reference mode, internal 500-Ω CW feedback resistor, CMOS CW clocks, at ambient temperature, T_A = 25°C, Digital demodulator is disabled unless otherwise noted. Min and max values are specified across full-temperature range with AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
TGC FULL SIGNAL CHANNEL (LNA + VCAT + LPF + ADC)
en (RTI)	Input voltage noise over LNA gain (low-noise mode)	Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 24 dB		0.76, 0.83, 1.16		nV/rtHz
	Input voltage noise over LNA gain (low-noise mode)	Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 30 dB		0.75, 0.86, 1.12		nV/rtHz
	Input voltage noise over LNA gain (low-power mode)	Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 24 dB		1.1, 1.2, 1.45		nV/rtHz
	Input voltage noise over LNA gain (low-power mode)	Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 30 dB		1.1, 1.2, 1.45		nV/rtHz
	Input voltage noise over LNA gain (medium-power mode)	Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 24 dB		1, 1.05, 1.25		nV/rtHz
	Input voltage noise over LNA gain (medium-power mode)	Rs = 0 Ω, ƒ = 2 MHz, LNA = 24, 18, 12 dB, PGA = 30 dB		0.95, 1, 1.2		nV/rtHz
en (RTI)	Input voltage noise at low frequency	ƒ = 100 kHz, INM capacitor = 1 µF, PGA integrator disabled		0.9		nV/rtHz
	Input referred current noise	Low-noise mode/medium-power mode/low-power mode		2.7, 2.1, 2		pA/rtHz
NF	Noise figure	Rs = 200 Ω, 200-Ω active termination, PGA = 24 dB, LNA = 12, 18, 24 dB		3.85, 2.4, 1.8		dB
NF	Noise figure	Rs = 100 Ω, 100-Ω active termination, PGA = 24 dB, LNA = 12, 18, 24 dB		5.3, 3.1, 2.3		dB
NF	Noise figure	Rs = 500 Ω, 1 kΩ, no termination, low-NF mode is enabled (Reg53[9] = 1)		0.94, 1.08		dB
NF	Noise figure	Rs = 50 Ω / 200 Ω, no termination, low-noise mode (Reg53[9] = 0)		2.35, 1.05		dB
V_MAX	Maximum linear input voltage	LNA gain = 24, 18, 12 dB		250, 500, 1000		mVpp
V_CLAMP	Clamp voltage	Reg52[10:9] = 0, LNA = 24, 18, 12 dB		350, 600, 1150		mVpp
	PGA gain	Low-noise mode		24, 30		dB
	PGA gain	Medium-power/low-power mode		24, 28.5		dB
	Total gain	LNA = 24 dB, PGA = 30 dB, low-noise mode		54		dB
		LNA = 24 dB, PGA = 30 dB, medium-power mode		52.5
		LNA = 24 dB, PGA = 30 dB, low-power mode		52.5
	Ch-CH noise correlation factor without signal ⁽²⁾	Summing of 8 channels		0
	Ch-CH noise correlation factor with signal ⁽²⁾	Full band (V_CNTL = 0, 0.8)		0.15, 0.17
	Ch-CH noise correlation factor with signal ⁽²⁾	1-MHz band over carrier (V_CNTL= 0, 0.8)		0.18, 0.75
	Signal-to-noise ratio (SNR)	V_CNTL= 0.6 V (22-dB total channel gain)	68	70		dBFS
		V_CNTL= 0, LNA = 18 dB, PGA = 24 dB	59.3	63
		V_CNTL= 0, LNA = 24 dB, PGA = 24 dB		58
	Narrow-band SNR	SNR over 2-MHz band around carrier at V_CNTL = 0.6 V (22-dB total gain)	75	77		dBFS
	Input common-mode voltage	At INP and INM pins		2.4		V
	Input resistance			8		kΩ
	Input resistance	Preset active termination enabled		50,100,200,400		Ω
	Input capacitance			20		pF
	Input control voltage	V_CNTLP – V_CNTLM	0		1.5	V
	Common-mode voltage	V_CNTLP and V_CNTLM		0.75		V
	Gain range			–40		dB
	Gain slope	V_CNTL= 0.1 to 1.1 V		35		dB/V
	Input resistance	Between V_CNTLP and V_CNTLM		200		kΩ
	Input capacitance	Between V_CNTLP and V_CNTLM		1		pF
	TGC response time	V_CNTL= 0- to 1.5-V step function		1.5		µs
	Third-order LPF			10, 15, 20, 30		MHz
	Settling time for change in LNA gain			14		µs
	Settling time for change in active termination setting			1		µs
AC ACCURACY
	LPF bandwidth tolerance			±5%
	CH-CH group delay variation	2 to 15 MHz		2		ns
	CH-CH phase variation	15-MHz signal		11		°
	Gain matching	0 V < V_CNTL< 0.1 V (Dev-to-Dev)		±0.5		dB
		0.1 V < V_CNTL< 1.1 V(Dev-to-Dev), T_A = 25°C	–1	±0.5	1
		1.1 V < V_CNTL< 1.5 V (Dev-to-Dev)		±0.5
		0.1 V < V_CNTL< 1.1 V (Dev-to-Dev), T_A = 0°C and 85°C	–1.1		1.1
	Gain matching	Channel-to-channel		±0.25		dB
	Output offset	V_CNTL= 0, PGA = 30 dB, LNA = 24 dB	–75		75	LSB
AC PERFORMANCE
HD2	Second-harmonic distortion	F_IN = 2 MHz; V_OUT = –1 dBFS		–60		dBc
		F_IN = 5 MHz; V_OUT = –1 dBFS		–60
		F_IN = 5 MHz; V_IN= 500 mV_PP, V_OUT = –1 dBFS, LNA = 18 dB, V_CNTL= 0.88 V		–55
		F_IN = 5 MHz; V_IN = 250 mV_PP, V_OUT = –1 dBFS, LNA = 24 dB, V_CNTL= 0.88 V		–55
HD3	Third-harmonic distortion	F_IN = 2 MHz; V_OUT = –1 dBFS		–55		dBc
		F_IN = 5 MHz; V_OUT = –1 dBFS		–55
		F_IN = 5 MHz; V_IN = 500 mV_PP, V_OUT = –1 dBFS, LNA = 18 dB, V_CNTL = 0.88 V		–55
		F_IN = 5 MHz; V_IN = 250 mV_PP, V_OUT = –1dBFS, LNA = 2 4dB, V_CNTL= 0.88 V		–55
THD	Total harmonic distortion	F_IN = 2 MHz; V_OUT = –1 dBFS		–55		dBc
THD	Total harmonic distortion	F_IN = 5 MHz; V_OUT = – 1dBFS		–55		dBc
IMD3	Intermodulation distortion	ƒ₁ = 5 MHz at –1 dBFS, ƒ₂ = 5.01 MHz at –27 dBFS		–60		dBc
XTALK	Cross-talk	F_IN = 5 MHz; V_OUT= –1 dBFS		–65		dB
	Phase noise	kHz off 5 MHz (V_CNTL= 0 V)		–132		dBc/Hz
LNA
	Input referred voltage noise	Rs = 0 Ω, ƒ = 2 MHz, Rin = High Z, Gain = 24, 18, 12 dB		0.63, 0.70, 0.9		nV/rtHz
	High-pass filter (HPF)	–3 dB cut-off frequency		50, 100, 150, 200		kHz
	LNA linear output			4		Vpp
VCAT+ PGA
	VCAT input noise	0-dB, –40-dB attenuation		2, 10.5		nV/rtHz
	PGA input noise	24 dB, 30 dB		1.75		nV/rtHz
	–3 dB HPF cut-off frequency			80		kHz
CW DOPPLER
en (RTI)	Input voltage noise (CW)	1-channel mixer, LNA = 24 dB, 500-Ω feedback resistor		0.8		nV/rtHz
en (RTI)	Input voltage noise (CW)	8-channel mixer, LNA = 24 dB, 62.5-Ω feedback resistor		0.33		nV/rtHz
en (RTO)	Output voltage noise (CW)	1-channel mixer, LNA = 24 dB, 500-Ω feedback resistor		12		nV/rtHz
en (RTO)	Output voltage noise (CW)	8-channel mixer, LNA = 24 dB, 62.5-Ω feedback resistor		5		nV/rtHz
en (RTI)	Input voltage noise (CW)	1-channel mixer, LNA = 18 dB, 500-Ω feedback resistor		1.1		nV/rtHz
en (RTI)	Input voltage noise (CW)	8-channel mixer, LNA = 18 dB, 62.5-Ω feedback resistor		0.5		nV/rtHz
en (RTO)	Output voltage noise (CW)	1-channel mixer, LNA = 18 dB, 500-Ω feedback resistor		8.1		nV/rtHz
en (RTO)	Output voltage noise (CW)	8-channel mixer, LNA = 18 dB, 62.5-Ω feedback resistor		4		nV/rtHz
NF	Noise figure	Rs = 100 Ω, R_IN = High Z, F_IN = 2 MHz (LNA, I/Q mixer and summing amplifier/filter)		1.8		dB
f_CW	CW operation range ⁽³⁾	CW signal carrier frequency		8		MHz
	CW clock frequency	1× CLK (16× mode)			8	MHz
		16× CLK(16× mode)			128
		4× CLK(4× mode)		32
	AC coupled LVDS clock amplitude	CLKM_16X-CLKP_16X; CLKM_1X-CLKP_1X		0.7		Vpp
	AC coupled LVPECL clock amplitude	CLKM_16X-CLKP_16X; CLKM_1X-CLKP_1X		1.6		Vpp
	CLK duty cycle	1× and 16× CLKs	35%		65%
	Common-mode voltage	Internal provided		2.5		V
V_CMOS	CMOS input clock amplitude		4		5	V
	CW mixer conversion loss			4		dB
	CW mixer phase noise	1 kHz off 2-MHz carrier		156		dBc/Hz
DR	Input dynamic range	F_IN = 2 MHz, LNA = 24/18/12 dB		160, 164, 165		dBFS/Hz
IMD3	Intermodulation distortion	ƒ₁ = 5 MHz, ƒ₂ = 5.01 MHz, both tones at –8.5-dBm amplitude, 8 channels summed up in-phase, CW feedback resistor = 87 Ω		–50		dBc
IMD3	Intermodulation distortion	ƒ₁ = 5 MHz, ƒ₂= 5.01 MHz, both tones at –8.5-dBm amplitude, single-channel case, CW feedback resistor = 500 Ω		–60		dBc
	I/Q channel gain matching	16× mode		±0.04		dB
	I/Q channel phase matching	16× mode		±0.1		°
	I/Q channel gain matching	4× mode		±0.04		dB
	I/Q channel phase matching	4× mode		±0.1		°
	Image rejection ratio	F_IN = 2.01 MHz, 300-mV input amplitude, CW clock frequency = 2 MHz		–50		dBc
CW SUMMING AMPLIFIER
V_CMO	Common-mode voltage	Summing amplifier inputs and outputs		1.5		V
	Summing amplifier output			4		Vpp
	Input referred voltage noise	100 Hz		2		nV/rtHz
		1 kHz		1.2		nV/rtHz
		2 kHz to 100 MHz		1		nV/rtHz
	Input referred current noise			2.5		pA/rtHz
	Unit gain bandwidth			200		MHz
	Max output current	Linear operation range		20		mApp
ADC SPECIFICATIONS
	Sample rate		10		65	MSPS
SNR	Signal-to-noise ratio	Idle channel SNR of ADC 14b		77		dBFS
	Internal reference mode	REFP		1.5		V
	Internal reference mode	REFM		0.5		V
	External reference mode	VREF_IN voltage		1.4		V
	External reference mode	VREF_IN current		50		µA
	ADC input full-scale range			2		Vpp
	LVDS rate	65 MSPS at 14 bit		910		Mbps
POWER DISSIPATION
	AVDD voltage		3.15	3.3	3.6	V
	AVDD_ADC voltage		1.7	1.8	1.9	V
	AVDD_5V voltage		4.75	5	5.5	V
	DVDD voltage		1.7	1.8	1.9	V
	Total power dissipation per channel	TGC low-noise mode, 65 MSPS		158	190	mW/CH
		TGC low-noise mode, 40 MSPS		145
		TGC medium-power mode, 40 MSPS		114
		TGC low-power mode, 40 MSPS		101.5
	AVDD (3.3-V) current	TGC low-noise mode, no signal		202	240	mA
		TGC medium-power mode, no signal		126
		TGC low-power mode, no signal		99
		CW-mode, no signal		147	170
		TGC low-noise mode, 500 mV_PP Input,1% duty cycle		210
		TGC medium-power mode, 500 mV_PP Input, 1% duty cycle		133
		TGC low power, 500 mV_PP Input, 1% duty cycle		105
		CW-mode, 500 mV_PP Input		375
	AVDD_5V current	TGC mode no signal		25.5	35	mA
		CW mode no signal, 16× clock = 32 MHz		32
		TGC mode, 500-mVpp Input,1% duty cycle		26
		CW-mode, 500-mVpp input		42.5
	VCA power dissipation	TGC low-noise mode, no signal		99	121	mW/CH
		TGC medium-power mode, no signal		68
		TGC low-power mode, no signal		55.5
		TGC low-noise mode, 500-mV_PP input,1% duty cycle		102.5
		TGC medium-power mode, 500-mV_PP Input, 1% duty cycle		71
		TGC low-power mode, 500-mVpp input,1% duty cycle		59.5
	CW power dissipation	No signal, ADC shutdown CW mode no signal, 16× clock = 32 MHz		80		mW/CH
	CW power dissipation	500-mV_PP input, ADC shutdown , 16× clock = 32 MHz		173		mW/CH
	AVDD_ADC (1.8-V) current	65MSPS		187	205	mA
	DVDD (1.8-V) current	65 MSPS		77	110	mA
	ADC power dissipation/CH	65 MSPS		59	69	mW/CH
		50 MSPS		51
		40 MSPS		46
		20 MSPS		35
	Power dissipation in power-down mode	PDN_VCA = High, PDN_ADC = High		25		mW/CH
	Power dissipation in power-down mode	Complete power-down PDN_Global = High		0.6		mW/CH
	Power-down response time	Time taken to enter power down		1		µs
	Power-up response time	VCA power down		2 µs + 1% of PDN time		µs
		ADC power down		1		µs
		Complete power down		2.5		ms
	Power supply modulation ratio, AVDD and AVDD_5V	F_IN = 5 MHz, at 50 mV_PP noise at 1 kHz on supply⁽¹⁾		–65		dBc
	Power supply modulation ratio, AVDD and AVDD_5V	F_IN = 5 MHz, at 50 mVpp noise at 50 kHz on supply⁽¹⁾		–65
	Power supply rejection ratio	ƒ = 10 kHz,V_CNTL = 0 V (high gain), AVDD		–40		dBc
		ƒ = 10 kHz,V_CNTL = 0 V (high gain), AVDD_5 V		–55		dBc
		ƒ = 10 kHz,V_CNTL = 1 V (low gain), AVDD		–50		dBc

(1) PSMR specification is with respect to carrier signal amplitude.

(2) Noise correlation factor is defined as Nc / (Nu + Nc), where Nc is the correlated noise power in single channel; and Nu is the uncorrelated noise power in single channel. Its measurement follows the below equation, in which the SNR of single-channel signal and the SNR of summed eight-channel signal are measured.
AFE5809 EQ_nc_los688.gif

(3) In the 16× operation mode, the CW operation range is limited to 8 MHz due to the 16× CLK. The maximum clock frequency for the 16× CLK is 128 MHz. In the 8×, 4×, and 1× modes, higher CW signal frequencies up to 15 MHz can be supported with small degradation in performance, see CW Clock Selection.

7.6 Digital Demodulator Electrical Characteristics

AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, DVDD_LDO = 1.4 V (internal generated), 14 bit/65 MSPS, 4× decimation factor, at ambient temperature T_A = 25°C, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Additional power consumption on DVDD (1.8 V)	65 MSPS, 4× decimation factor		90		mW/CH
	Additional power consumption on DVDD (1.8 V)	40 MSPS, 4× decimation factor		61		mW/CH
	Additional power consumption on DVDD (1.8 V)	65 MSPS, 32× decimation factor, half LVDS pairs are powered down		77		mW/CH
	Additional power consumption on DVDD (1.8 V)	40 MSPS, 32× decimation factor, half LVDS pairs are powered down		55		mW/CH
V_IH	Logic high input voltage, TX_SYNC pin	Support 1.8-V and 3.3-V CMOS logic	1.3		3.3	V
V_IL	Logic low input voltage, TX_SYNC pin	Support 1.8-V and 3.3-V CMOS logic	0		0.3	V
I_IH	Logic high input current, TX_SYNC pin	V_HIGH = 1.8 V		11		µA
I_IL	Logic low input current, TX_SYNC pin	V_LOW = 0 V		< 0.1		µA
V_IH	Logic high input voltage, LDO_EN pin		1.7		3.3	V
V_IL	Logic low input voltage, LDO_EN pin		0		0.3	V
I_IH	Logic high input current, LDO_EN pin	V_HIGH = 1.8 V		11		µA
I_IL	Logic low input current, LDO_EN pin	V_LOW = 0 V		< 0.1		µA

7.7 Digital Characteristics

Typical values are at 25°C, AVDD = 3.3 V, AVDD_5 = 5 V and AVDD_ADC = 1.8 V, DVDD = 1.8 V unless otherwise noted. Minimum and maximum values are across the full temperature range: T_MIN = 0°C to T_MAX = 85°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT⁽¹⁾
DIGITAL INPUTS/OUTPUTS
V_IH	Logic high input voltage		2		3.3	V
V_IL	Logic low input voltage		0		0.3	V
	Logic high input current			200		µA
	Logic low input current			200		µA
	Input capacitance			5		pF
V_OH	Logic high output voltage	SDOUT pin		DVDD		V
V_OL	Logic low output voltage	SDOUT pin		0		V
LVDS OUTPUTS
	Output differential voltage	With 100-Ω external differential termination		400		mV
	Output offset voltage	Common-mode voltage		1100		mV
	FCLKP and FCLKM	1× clock rate	10		65	MHz
	DCLKP and DCLKM	7× clock rate	70		455	MHz
		6× clock rate	60		390	MHz
t_su	Data setup time⁽²⁾			350		ps
t_h	Data hold time⁽²⁾			350		ps
ADC INPUT CLOCK
	Clock frequency		10		65	MSPS
	Clock duty cycle		45%	50%	55%
	Clock input amplitude, differential(V_{CLKP_ADC} – V_{CLKM_ADC})	Sine-wave, AC-coupled	0.5			Vpp
		LVPECL, AC-coupled		1.6		Vpp
		LVDS, AC-coupled		0.7		Vpp
	Common-mode voltage	Biased internally		1		V
	Clock input amplitude V_{CLKP_ADC} (single-ended)	CMOS clock		1.8		Vpp

(1) The DC specifications refer to the condition where the LVDS outputs are not switching, but are permanently at a valid logic level 0 or 1 with 100-Ω external termination.

(2) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume that the data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as reduced timing margins

7.8 Switching Characteristics

AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V. Typical values are at 25°C, Differential clock, C_LOAD = 5 pF, R_LOAD = 100 Ω, 14 bit, sample rate = 65 MSPS, digital demodulator is disabled, unless otherwise noted. Minimum and maximum values are across the full temperature range T_MIN = 0°C to T_MAX = 85°C.⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_a	Aperture delay	The delay in time between the rising edge of the input sampling clock and the actual time at which the sampling occurs.	0.7	3		ns
	Aperture delay matching	Across channels within the same device		±150		ps
t_j	Aperture jitter			450		Fs rms
	ADC latency	Default, after reset, or / 0 x 2 [12] = 1, LOW_LATENCY = 1		11/8		Input clock cycles
t_delay	Data and frame clock delay	Input clock rising edge (zero cross) to frame clock rising edge (zero cross) minus 3/7 of the input clock period (T)	3	5.4	7	ns
Δt_delay	Delay variation	At fixed supply and 20°C T difference; device to device	–1		1	ns
t_RISE	Data rise time	Rise time measured from –100 to 100 mV		0.14		ns
t_FALL	Data fall time	Fall time measured from 100 to –100 mV 10 MHz < ƒ_CLKIN < 65 MHz		0.15		ns
t_FCLKRISE	Frame clock rise time	Rise time measured from –100 to 100 mV		0.14		ns
t_FCLKFALL	Frame clock fall time	Fall time measured from 100 to –100 mV 10 MHz < ƒ_CLKIN < 65 MHz		0.15		ns
	Frame clock duty cycle	Zero crossing of the rising edge to zero crossing of the falling edge	48%	50%	52%
t_DCLKRISE	Bit clock rise time	Rise time measured from –100 to 100 mV		0.13		ns
t_DCLKFALL	Bit clock fall time	Fall time measured from 100 to –100 mV 10 MHz < ƒ_CLKIN < 65 MHz		0.12		ns
	Bit clock duty cycle	Zero crossing of the rising edge to zero crossing of the falling edge 10 MHz < ƒ_CLKIN < 65 MHz	46%		54%

(1) Timing parameters are ensured by design and characterization; not production tested.

7.9 SPI Switching Characteristics

Minimum values across full temperature range T_MIN = 0°C to T_MAX = 85°C, AVDD_5V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V

PARAMETER		MIN	TYP	MAX	UNIT
t₁	SCLK period	50			ns
t₂	SCLK high time	20			ns
t₃	SCLK low time	20			ns
t₄	Data setup time	5			ns
t₅	Data hold time	5			ns
t₆	SEN fall to SCLK rise	8			ns
t₇	Time between last SCLK rising edge to SEN rising edge	8			ns
t₈	SDOUT delay	12	20	28	ns

7.10 Output Interface Timing Requirements (14-bit)

ƒ_CLKIN, Input Clock Frequency⁽¹⁾⁽²⁾⁽³⁾	Setup Time (t_su), ns			Hold Time (t_h), ns			t_PROG = (3/7) × T + t_delay, ns
ƒ_CLKIN, Input Clock Frequency⁽¹⁾⁽²⁾⁽³⁾	Data Valid to Bit Clock Zero-Crossing			Bit Clock Zero-Crossing to Data Invalid			Input Clock Zero-Cross (Rising Edge) to Frame Clock Zero-Cross (Rising Edge)
MHz	MIN	TYP	MAX	MIN	TYP	MAX	MIN	TYP	MAX
65	0.24	0.37		0.24	0.38		11	12	12.5
50	0.41	0.54		0.46	0.57		13	13.9	14.4
40	0.55	0.70		0.61	0.73		15	16	16.7
30	0.87	1.10		0.94	1.1		18.5	19.5	20.1
20	1.30	1.56		1.46	1.6		25.7	26.7	27.3

(1) FCLK timing is the same as for the output data lines. It has the same relation to DCLK as the data pins. Setup and hold are the same for the data and frame clock.

(2) Data valid is logic high = 100 mV and logic low = –100 mV

(3) Timing parameters are ensured by design and characterization; not production tested.

SPACER

NOTE

The data from Output Interface Timing Requirements (14-bit) can be applied to 12-bit or 16-bit LVDS rates as well. For example, the maximum LVDS output rate at 65 MHz and 14-bit is equal to 910 MSPS, which is approximately equivalent to the rate at 56 MHz and 16 bits.

Figure 1. LVDS Timing Diagrams

7.11 Typical Characteristics

AVDD_5 V = 5 V, AVDD = 3.3 V, AVDD_ADC = 1.8 V, DVDD = 1.8 V, AC-coupled with 0.1-µF capacitors at INP and 15-nF capacitors at INM, No active termination, V_CNTL = 0 V, F_IN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 bit, sample rate = 65 MSPS, LPF filter = 15 MHz, low-noise mode, Single-ended V_CNTL mode, V_CNTLM = GND, ADC is configured in internal reference mode, V_OUT = –1 dBFS, 500-Ω CW feedback resistor, CMOS 16× clock, digital demodulator is disabled, at ambient temperature T_A = 25°C, unless otherwise noted.

Figure 2. Gain vs V_CNTL, LNA = 18 dB and PGA = 24 dB

Figure 4. Gain Matching Histogram, V_CNTL = 0.3 V (34951 Channels)

Figure 6. Gain Matching Histogram, V_CNTL = 0.9 V (34951 Channels)

AFE5809 gr_input_impedance_mag_response_open_LOS738.gif

Figure 8. Input Impedance Without Active Termination (Magnitude)

AFE5809 gr_input_impedance_mag_response_LOS738.gif

Figure 10. Input Impedance With Active Termination (Magnitude)

Figure 12. LPF Response

Figure 14. Full Channel HPF Response at Default Register Setting

Figure 16. CW Phase Noise, F_IN = 2 MHz, 1 Channel vs 8 Channel

Figure 18. IRN, PGA = 24 dB and Low Noise Mode

Figure 20. IRN, PGA = 24 dB and Medium-Power Mode

Figure 22. IRN, PGA = 24 dB and Low-Power Mode

Figure 24. ORN, PGA = 24 dB and Low Noise Mode

Figure 26. ORN, PGA = 24 dB and Low-Power Mode

Figure 28. ORN, PGA = 24 dB and Low Noise Mode

Figure 30. SNR, LNA = 18 dB and Low-Power Mode

Figure 32. Noise Figure, LNA = 12 dB and Low Noise Mode

Figure 34. Noise Figure, LNA = 24 dB and Low Noise Mode

Figure 36. Noise Figure vs Power Modes Without Termination

Figure 38. HD3 vs Frequency, V_IN = 500 mVpp and
V_OUT = –1 dBFS

Figure 40. HD3 vs Gain, LNA = 12 dB and PGA = 24 dB and V_OUT = –1 dBFS

Figure 42. HD3 vs Gain, LNA = 18 dB and PGA = 24 dB and V_OUT = –1 dBFS

Figure 44. HD3 vs Gain, LNA = 24 dB and PGA = 24 dB and V_OUT = –1 dBFS

Figure 46. IMD3, Fout1 = –7 dBFS and Fout2 = –7 dBFS

Figure 48. AVDD_5V Power Supply Modulation Ratio,
100 mVpp Supply Noise With Different Frequencies

Figure 50. AVDD_5V Power Supply Rejection Ratio,
100 mVpp Supply Noise With Different Frequencies

AFE5809 Figure 53 Vcon_rising_step_response.png

Figure 52. V_CNTL Response Time, LNA = 18 dB and
PGA = 24 dB

Figure 54. Pulse Inversion Asymmetrical Negative Input

Figure 56. Overload Recovery Response vs INM Capacitor, V_IN = 50 mVpp/100 µVpp, Max Gain

Figure 58. Digital HPF Response

Figure 3. Gain Variation vs Temperature, LNA = 18 dB and PGA = 24 dB

Figure 5. Gain Matching Histogram, V_CNTL = 0.6 V (34951 Channels)

Figure 7. Output Offset Histogram, V_CNTL = 0 V (1247 Channels)

AFE5809 gr_input_impedance_phase_response_open_LOS738.gif

Figure 9. Input Impedance Without Active Termination (Phase)

AFE5809 gr_input_impedance_phase_response_LOS738.gif

Figure 11. Input Impedance With Active Termination (Phase)

Figure 13. LNA HPF Response vs Reg59[3:2]

Figure 15. CW Phase Noise, F_IN = 2 MHz

Figure 17. CW Phase Noise vs Clock Modes, F_IN= 2 MHz

Figure 19. IRN, PGA = 24 dB and Low Noise Mode

Figure 21. IRN, PGA = 24 dB and Medium-Power Mode

Figure 23. IRN, PGA = 24 dB and Low-Power Mode

Figure 25. ORN, PGA = 24 dB and Medium-Power Mode

Figure 27. IRN, PGA = 24 dB and Low Noise Mode

Figure 29. SNR, LNA = 18 dB and Low Noise Mode

Figure 31. SNR vs Different Power Modes

Figure 33. Noise Figure, LNA = 18 dB and Low Noise Mode

Figure 35. Noise Figure vs Power Modes With 400-Ω Termination

Figure 37. HD2 vs Frequency, V_IN = 500 mVpp and
V_OUT = –1 dBFS

Figure 39. HD2 vs Gain, LNA = 12 dB and PGA = 24 dB and V_OUT = –1 dBFS

Figure 41. HD2 vs Gain, LNA = 18 dB and PGA = 24 dB and V_OUT = –1 dBFS

Figure 43. HD2 vs Gain, LNA = 24 dB and PGA = 24 dB and V_OUT = –1 dBFS

Figure 45. IMD3, Fout1 = –7 dBFS and Fout2 = –21 dBFS

Figure 47. AVDD Power Supply Modulation Ratio, 100 mVpp Supply Noise With Different Frequencies

Figure 49. AVDD Power Supply Rejection Ratio, 100 mVpp Supply Noise With Different Frequencies

AFE5809 Figure 52 Vcon_falling_step_response.png

Figure 51. V_CNTL Response Time, LNA = 18 dB and
PGA = 24 dB

Figure 53. Pulse Inversion Asymmetrical Positive Input

Figure 55. Pulse Inversion, V_IN = 2 Vpp, PRF = 1 kHz,
Gain = 21 dB

AFE5809 Figure 58 100dB_overload_zoomed.png

Figure 57. Overload Recovery Response vs INM Capacitor (Zoomed), V_IN = 50 mVpp/100 µVpp, Max Gain

Figure 59. Signal Chain Low Frequency Response With INM Capacitor = 1 µF