ZHCSHP8B December   2017  – January 2019 AMIC120

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
      1. Table 4-1 ZDN Ball Map [Section Top Left - Top View]
      2. Table 4-2 ZDN Ball Map [Section Top Middle - Top View]
      3. Table 4-3 ZDN Ball Map [Section Top Right - Top View]
      4. Table 4-4 ZDN Ball Map [Section Middle Left - Top View]
      5. Table 4-5 ZDN Ball Map [Section Middle Middle - Top View]
      6. Table 4-6 ZDN Ball Map [Section Middle Right - Top View]
      7. Table 4-7 ZDN Ball Map [Section Bottom Left - Top View]
      8. Table 4-8 ZDN Ball Map [Section Bottom Middle - Top View]
      9. Table 4-9 ZDN Ball Map [Section Bottom Right - Top View]
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  ADC Interfaces
      2. 4.3.2  CAN Interfaces
      3. 4.3.3  Debug Subsystem Interface
      4. 4.3.4  Ethernet (GEMAC_CPSW) Interfaces
      5. 4.3.5  External Memory Interfaces
      6. 4.3.6  General Purpose IOs
      7. 4.3.7  HDQ Interface
      8. 4.3.8  I2C Interfaces
      9. 4.3.9  McASP Interfaces
      10. 4.3.10 Miscellaneous
      11. 4.3.11 PRU-ICSS0 Interface
      12. 4.3.12 PRU-ICSS1 Interface
      13. 4.3.13 QSPI Interface
      14. 4.3.14 RTC Subsystem Interface
      15. 4.3.15 Removable Media Interfaces
      16. 4.3.16 SPI Interfaces
      17. 4.3.17 Timer Interfaces
      18. 4.3.18 UART Interfaces
      19. 4.3.19 USB Interfaces
      20. 4.3.20 eCAP Interfaces
      21. 4.3.21 eHRPWM Interfaces
      22. 4.3.22 eQEP Interfaces
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH)
    4. 5.4  Operating Performance Points
    5. 5.5  Recommended Operating Conditions
    6. 5.6  Power Consumption Summary
    7. 5.7  DC Electrical Characteristics
    8. 5.8  ADC0: Analog-to-Digital Subsystem Electrical Parameters
    9. 5.9  Thermal Resistance Characteristics
      1. Table 5-6 Thermal Resistance Characteristics (NFBGA Package) [ZDN]
    10. 5.10 External Capacitors
      1. 5.10.1 Voltage Decoupling Capacitors
        1. 5.10.1.1 Core Voltage Decoupling Capacitors
        2. 5.10.1.2 IO and Analog Voltage Decoupling Capacitors
      2. 5.10.2 Output Capacitors
    11. 5.11 Timing and Switching Characteristics
      1. 5.11.1  Power Supply Sequencing
        1. 5.11.1.1 Power Supply Slew Rate Requirement
        2. 5.11.1.2 Power-Up Sequencing
        3. 5.11.1.3 Power-Down Sequencing
      2. 5.11.2  Clock
        1. 5.11.2.1 PLLs
          1. 5.11.2.1.1 Digital Phase-Locked Loop Power Supply Requirements
        2. 5.11.2.2 Input Clock Specifications
        3. 5.11.2.3 Input Clock Requirements
          1. 5.11.2.3.1 OSC0 Internal Oscillator Clock Source
            1. Table 5-11 OSC0 Crystal Circuit Requirements
            2. Table 5-12 OSC0 Crystal Circuit Characteristics
          2. 5.11.2.3.2 OSC0 LVCMOS Digital Clock Source
          3. 5.11.2.3.3 OSC1 Internal Oscillator Clock Source
            1. Table 5-14 OSC1 Crystal Circuit Requirements
            2. Table 5-15 OSC1 Crystal Circuit Characteristics
          4. 5.11.2.3.4 OSC1 LVCMOS Digital Clock Source
          5. 5.11.2.3.5 OSC1 Not Used
        4. 5.11.2.4 Output Clock Specifications
        5. 5.11.2.5 Output Clock Characteristics
          1. 5.11.2.5.1 CLKOUT1
          2. 5.11.2.5.2 CLKOUT2
      3. 5.11.3  Timing Parameters and Board Routing Analysis
      4. 5.11.4  Recommended Clock and Control Signal Transition Behavior
      5. 5.11.5  Controller Area Network (CAN)
        1. 5.11.5.1 DCAN Electrical Data and Timing
          1. Table 5-17 Timing Requirements for DCANx Receive
          2. Table 5-18 Switching Characteristics for DCANx Transmit
      6. 5.11.6  DMTimer
        1. 5.11.6.1 DMTimer Electrical Data and Timing
          1. Table 5-19 Timing Requirements for DMTimer [1-11]
          2. Table 5-20 Switching Characteristics for DMTimer [4-7]
      7. 5.11.7  Ethernet Media Access Controller (EMAC) and Switch
        1. 5.11.7.1 Ethernet MAC and Switch Electrical Data and Timing
          1. Table 5-21 Ethernet MAC and Switch Timing Conditions
          2. 5.11.7.1.1 Ethernet MAC/Switch MDIO Electrical Data and Timing
            1. Table 5-22 Timing Requirements for MDIO_DATA
            2. Table 5-23 Switching Characteristics for MDIO_CLK
            3. Table 5-24 MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.7.1.2 Ethernet MAC and Switch MII Electrical Data and Timing
            1. Table 5-25 Timing Requirements for GMII[x]_RXCLK - MII Mode
            2. Table 5-26 Timing Requirements for GMII[x]_TXCLK - MII Mode
            3. Table 5-27 Timing Requirements for GMII[x]_RXD[3:0], GMII[x]_RXDV, and GMII[x]_RXER - MII Mode
            4. Table 5-28 Switching Characteristics for GMII[x]_TXD[3:0], and GMII[x]_TXEN - MII Mode
          4. 5.11.7.1.3 Ethernet MAC and Switch RMII Electrical Data and Timing
            1. Table 5-29 Timing Requirements for RMII[x]_REFCLK - RMII Mode
            2. Table 5-30 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER - RMII Mode
            3. Table 5-31 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN - RMII Mode
          5. 5.11.7.1.4 Ethernet MAC and Switch RGMII Electrical Data and Timing
            1. Table 5-32 Timing Requirements for RGMII[x]_RCLK - RGMII Mode
            2. Table 5-33 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL - RGMII Mode
            3. Table 5-34 Switching Characteristics for RGMII[x]_TCLK - RGMII Mode
            4. Table 5-35 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TCTL - RGMII Mode
      8. 5.11.8  External Memory Interfaces
        1. 5.11.8.1 General-Purpose Memory Controller (GPMC)
          1. 5.11.8.1.1 GPMC and NOR Flash—Synchronous Mode
            1. Table 5-36 GPMC and NOR Flash Timing Conditions—Synchronous Mode
            2. Table 5-37 GPMC and NOR Flash Timing Requirements—Synchronous Mode
            3. Table 5-38 GPMC and NOR Flash Switching Characteristics—Synchronous Mode
          2. 5.11.8.1.2 GPMC and NOR Flash—Asynchronous Mode
            1. Table 5-39 GPMC and NOR Flash Timing Conditions—Asynchronous Mode
            2. Table 5-40 GPMC and NOR Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-41 GPMC and NOR Flash Timing Requirements—Asynchronous Mode
            4. Table 5-42 GPMC and NOR Flash Switching Characteristics—Asynchronous Mode
          3. 5.11.8.1.3 GPMC and NAND Flash—Asynchronous Mode
            1. Table 5-43 GPMC and NAND Flash Timing Conditions—Asynchronous Mode
            2. Table 5-44 GPMC and NAND Flash Internal Timing Parameters—Asynchronous Mode
            3. Table 5-45 GPMC and NAND Flash Timing Requirements—Asynchronous Mode
            4. Table 5-46 GPMC and NAND Flash Switching Characteristics—Asynchronous Mode
        2. 5.11.8.2 Memory Interface
          1. 5.11.8.2.1 DDR3 and DDR3L Routing Guidelines
            1. 5.11.8.2.1.1 Board Designs
            2. 5.11.8.2.1.2 DDR3 Device Combinations
            3. 5.11.8.2.1.3 DDR3 Interface
              1. 5.11.8.2.1.3.1  DDR3 Interface Schematic
              2. 5.11.8.2.1.3.2  Compatible JEDEC DDR3 Devices
              3. 5.11.8.2.1.3.3  DDR3 PCB Stackup
              4. 5.11.8.2.1.3.4  DDR3 Placement
              5. 5.11.8.2.1.3.5  DDR3 Keepout Region
              6. 5.11.8.2.1.3.6  DDR3 Bulk Bypass Capacitors
              7. 5.11.8.2.1.3.7  DDR3 High-Speed Bypass Capacitors
                1. 5.11.8.2.1.3.7.1 Return Current Bypass Capacitors
              8. 5.11.8.2.1.3.8  DDR3 Net Classes
              9. 5.11.8.2.1.3.9  DDR3 Signal Termination
              10. 5.11.8.2.1.3.10 DDR3 DDR_VREF Routing
              11. 5.11.8.2.1.3.11 DDR3 VTT
            4. 5.11.8.2.1.4 DDR3 CK and ADDR_CTRL Topologies and Routing Definition
              1. 5.11.8.2.1.4.1 Using Two DDR3 Devices (x8 or x16)
                1. 5.11.8.2.1.4.1.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
                2. 5.11.8.2.1.4.1.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
              2. 5.11.8.2.1.4.2 Using Four 8-Bit DDR3 Devices
                1. 5.11.8.2.1.4.2.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
                2. 5.11.8.2.1.4.2.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
              3. 5.11.8.2.1.4.3 One 16-Bit DDR3 Device
                1. 5.11.8.2.1.4.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
                2. 5.11.8.2.1.4.3.2 CK and ADDR_CTRL Routing, One DDR3 Device
            5. 5.11.8.2.1.5 Data Topologies and Routing Definition
              1. 5.11.8.2.1.5.1 DQS[x] and DQ[x] Topologies, Any Number of Allowed DDR3 Devices
              2. 5.11.8.2.1.5.2 DQS[x] and DQ[x] Routing, Any Number of Allowed DDR3 Devices
            6. 5.11.8.2.1.6 Routing Specification
              1. 5.11.8.2.1.6.1 CK and ADDR_CTRL Routing Specification
              2. 5.11.8.2.1.6.2 DQS[x] and DQ[x] Routing Specification
          2. 5.11.8.2.2 LPDDR2 Routing Guidelines
            1. 5.11.8.2.2.1 LPDDR2 Board Designs
            2. 5.11.8.2.2.2 LPDDR2 Device Configurations
            3. 5.11.8.2.2.3 LPDDR2 Interface
              1. 5.11.8.2.2.3.1 LPDDR2 Interface Schematic
              2. 5.11.8.2.2.3.2 Compatible JEDEC LPDDR2 Devices
              3. 5.11.8.2.2.3.3 LPDDR2 PCB Stackup
              4. 5.11.8.2.2.3.4 LPDDR2 Placement
              5. 5.11.8.2.2.3.5 LPDDR2 Keepout Region
              6. 5.11.8.2.2.3.6 LPDDR2 Net Classes
              7. 5.11.8.2.2.3.7 LPDDR2 Signal Termination
              8. 5.11.8.2.2.3.8 LPDDR2 DDR_VREF Routing
            4. 5.11.8.2.2.4 Routing Specification
              1. 5.11.8.2.2.4.1 DQS[x] and DQ[x] Routing Specification
              2. 5.11.8.2.2.4.2 CK and ADDR_CTRL Routing Specification
      9. 5.11.9  Display Subsystem (DSS)
      10. 5.11.10 Camera (VPFE)
      11. 5.11.11 Inter-Integrated Circuit (I2C)
        1. 5.11.11.1 I2C Electrical Data and Timing
          1. Table 5-69 I2C Timing Conditions - Slave Mode
          2. Table 5-70 Timing Requirements for I2C Input Timings
          3. Table 5-71 Switching Characteristics for I2C Output Timings
      12. 5.11.12 Multichannel Audio Serial Port (McASP)
        1. 5.11.12.1 McASP Device-Specific Information
        2. 5.11.12.2 McASP Electrical Data and Timing
          1. Table 5-72 McASP Timing Conditions
          2. Table 5-73 Timing Requirements for McASP
          3. Table 5-74 Switching Characteristics for McASP
      13. 5.11.13 Multichannel Serial Port Interface (McSPI)
        1. 5.11.13.1 McSPI Electrical Data and Timing
          1. 5.11.13.1.1 McSPI—Slave Mode
            1. Table 5-75 McSPI Timing Conditions—Slave Mode
            2. Table 5-76 Timing Requirements for McSPI Input Timings—Slave Mode
            3. Table 5-77 Switching Characteristics for McSPI Output Timings—Slave Mode
          2. 5.11.13.1.2 McSPI—Master Mode
            1. Table 5-78 McSPI Timing Conditions—Master Mode
            2. Table 5-79 Timing Requirements for McSPI Input Timings—Master Mode
            3. Table 5-80 Switching Characteristics for McSPI Output Timings—Master Mode
      14. 5.11.14 Quad Serial Port Interface (QSPI)
        1. Table 5-81 QSPI Switching Characteristics
      15. 5.11.15 HDQ/1-Wire Interface (HDQ/1-Wire)
        1. 5.11.15.1 HDQ Protocol
        2. 5.11.15.2 1-Wire Protocol
      16. 5.11.16 Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
        1. 5.11.16.1 Programmable Real-Time Unit (PRU-ICSS PRU)
          1. Table 5-86  PRU-ICSS PRU Timing Conditions
          2. 5.11.16.1.1 PRU-ICSS PRU Direct Input/Output Mode Electrical Data and Timing
            1. Table 5-87 PRU-ICSS PRU Timing Requirements - Direct Input Mode
            2. Table 5-88 PRU-ICSS PRU Switching Requirements - Direct Output Mode
          3. 5.11.16.1.2 PRU-ICSS PRU Parallel Capture Mode Electrical Data and Timing
            1. Table 5-89 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
          4. 5.11.16.1.3 PRU-ICSS PRU Shift Mode Electrical Data and Timing
            1. Table 5-90 PRU-ICSS PRU Timing Requirements - Shift In Mode
            2. Table 5-91 PRU-ICSS PRU Switching Requirements - Shift Out Mode
          5. 5.11.16.1.4 PRU-ICSS Sigma Delta Electrical Data and Timing
            1. Table 5-92 PRU-ICSS Timing Requirements - Sigma Delta Mode
          6. 5.11.16.1.5 PRU-ICSS ENDAT Electrical Data and Timing
            1. Table 5-93 PRU-ICSS Timing Requirements - ENDAT Mode
            2. Table 5-94 PRU-ICSS Switching Requirements - ENDAT Mode
        2. 5.11.16.2 PRU-ICSS EtherCAT (PRU-ICSS ECAT)
          1. Table 5-95  PRU-ICSS ECAT Timing Conditions
          2. 5.11.16.2.1 PRU-ICSS ECAT Electrical Data and Timing
            1. Table 5-96  PRU-ICSS ECAT Timing Requirements - Input Validated With LATCH_IN
            2. Table 5-97  PRU-ICSS ECAT Timing Requirements - Input Validated With SYNCx
            3. Table 5-98  PRU-ICSS ECAT Timing Requirements - Input Validated With Start of Frame (SOF)
            4. Table 5-99  PRU-ICSS ECAT Timing Requirements - LATCHx_IN
            5. Table 5-100 PRU-ICSS ECAT Switching Requirements - Digital IOs
        3. 5.11.16.3 PRU-ICSS MII_RT and Switch
          1. Table 5-101 PRU-ICSS MII_RT Switch Timing Conditions
          2. 5.11.16.3.1 PRU-ICSS MDIO Electrical Data and Timing
            1. Table 5-102 PRU-ICSS MDIO Timing Requirements - MDIO_DATA
            2. Table 5-103 PRU-ICSS MDIO Switching Characteristics - MDIO_CLK
            3. Table 5-104 PRU-ICSS MDIO Switching Characteristics - MDIO_DATA
          3. 5.11.16.3.2 PRU-ICSS MII_RT Electrical Data and Timing
            1. Table 5-105 PRU-ICSS MII_RT Timing Requirements - MII_RXCLK
            2. Table 5-106 PRU-ICSS MII_RT Timing Requirements - MII[x]_TXCLK
            3. Table 5-107 PRU-ICSS MII_RT Timing Requirements - MII_RXD[3:0], MII_RXDV, and MII_RXER
            4. Table 5-108 PRU-ICSS MII_RT Switching Characteristics - MII_TXD[3:0] and MII_TXEN
        4. 5.11.16.4 PRU-ICSS Universal Asynchronous Receiver Transmitter (PRU-ICSS UART)
          1. Table 5-109 Timing Requirements for PRU-ICSS UART Receive
          2. Table 5-110 Switching Characteristics Over Recommended Operating Conditions for PRU-ICSS UART Transmit
      17. 5.11.17 Multimedia Card (MMC) Interface
        1. 5.11.17.1 MMC Electrical Data and Timing
          1. Table 5-111 MMC Timing Conditions
          2. Table 5-112 Timing Requirements for MMC[0]_CMD and MMC[0]_DAT[7:0]
          3. Table 5-113 Timing Requirements for MMC[1/2]_CMD and MMC[1/2]_DAT[7:0]
          4. Table 5-114 Switching Characteristics for MMC[x]_CLK
          5. Table 5-115 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=0
          6. Table 5-116 Switching Characteristics for MMC[x]_CMD and MMC[x]_DAT[7:0]—HSPE=1
      18. 5.11.18 Universal Asynchronous Receiver/Transmitter (UART)
        1. 5.11.18.1 UART Electrical Data and Timing
          1. Table 5-117 Timing Requirements for UARTx Receive
          2. Table 5-118 for UARTx Transmit
        2. 5.11.18.2 UART IrDA Interface
    12. 5.12 Emulation and Debug
      1. 5.12.1 IEEE 1149.1 JTAG
        1. 5.12.1.1 JTAG Electrical Data and Timing
          1. Table 5-121 Timing Requirements for JTAG
          2. Table 5-122 Switching Characteristics for JTAG
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
    4. 6.4 Community Resources
    5. 6.5 商标
    6. 6.6 静电放电警告
    7. 6.7 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Via Channel
    2. 7.2 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZDN|491
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.2 Pin Attributes

  1. BALL NUMBER: Package ball numbers associated with each signals.
  2. PIN NAME: The name of the package pin.
    Note: The table does not take into account subsystem terminal multiplexing options.
  3. SIGNAL NAME: The signal name for that pin in the mode being used.
  4. MODE: Multiplexing mode number.
    1. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the terminal corresponds to the name of the terminal. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode.

      2. Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE column.

    2. Modes 1 to 7 are possible modes for alternate functions. On each terminal, some modes are effectively used for alternate functions, while some modes are not used and do not correspond to a functional configuration.
  5. TYPE: Signal direction
    • I = Input
    • O = Output
    • IO = Input and Output
    • D = Open drain
    • DS = Differential
    • A = Analog
    • PWR = Power
    • GND = Ground

      • Note: In the safe_mode, the buffer is configured in high-impedance.

  6. BALL RESET STATE: State of the terminal while the active low PWRONRSTn terminal is low.
    • 0: The buffer drives VOL (pulldown or pullup resistor not activated)
      0(PD): The buffer drives VOL with an active pulldown resistor
    • 1: The buffer drives VOH (pulldown or pullup resistor not activated)
      1(PU): The buffer drives VOH with an active pullup resistor
    • Z or OFF: High-impedance
    • L: High-impedance with an active pulldown resistor
    • H : High-impedance with an active pullup resistor
  7. BALL RESET REL. STATE: State of the terminal after the active low PWRONRSTn terminal transitions from low to high.
    • 0: The buffer drives VOL (pulldown or pullup resistor not activated)
      0(PD): The buffer drives VOL with an active pulldown resistor
    • 1: The buffer drives VOH (pulldown or pullup resistor not activated)
      1(PU): The buffer drives VOH with an active pullup resistor
    • Z or OFF: High-impedance.
    • L: High-impedance with an active pulldown resistor
    • H : High-impedance with an active pullup resistor
  8. RESET REL. MODE: The mode is automatically configured after the active low PWRONRSTn terminal transitions from low to high.
  9. POWER: The voltage supply that powers the terminal’s IO buffers.
  10. HYS: Indicates if the input buffer is with hysteresis.
  11. BUFFER STRENGTH: Drive strength of the associated output buffer.
  12. PULLUP OR PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
  13. IO CELL: IO cell information.

    14. Note: Configuring two terminals to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration.

CAUTION

Not all exposed peripherals are supported on the AMIC120 device. Refer to Table 3-1, Device Comparison Table, for details on supported peripherals.

Table 4-10 Pin Attributes (ZDN Package)

BALL NUMBER [1] PIN NAME [2] SIGNAL NAME [3] MODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MODE [8] POWER [9] HYS [10] BUFFER STRENGTH (mA) [11] PULL UP/DOWN TYPE [12] IO CELL [13]
AE14 ADC0_VREFN ADC0_VREFN 0x0 AP Z Z Mode0 VDDA_ADC0 NA NA NA Analog
AD14 ADC0_VREFP ADC0_VREFP 0x0 AP Z Z Mode0 VDDA_ADC0 NA NA NA Analog
AD15 ADC1_VREFN ADC1_VREFN 0x0 AP Z Z Mode0 VDDA_ADC1 NA NA NA Analog
AE15 ADC1_VREFP ADC1_VREFP 0x0 AP Z Z Mode0 VDDA_ADC1 NA NA NA Analog
AA12 ADC0_AIN0 ADC0_AIN0 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
Y12 ADC0_AIN1 ADC0_AIN1 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
Y13 ADC0_AIN2 ADC0_AIN2 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
AA13 ADC0_AIN3 ADC0_AIN3 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
AB13 ADC0_AIN4 ADC0_AIN4 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
AC13 ADC0_AIN5 ADC0_AIN5 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
AD13 ADC0_AIN6 ADC0_AIN6 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
AE13 ADC0_AIN7 ADC0_AIN7 0x0 A Z Z Mode0 VDDA_ADC0 NA 25 NA Analog
AC16 ADC1_AIN0 ADC1_AIN0 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AB16 ADC1_AIN1 ADC1_AIN1 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AA16 ADC1_AIN2 ADC1_AIN2 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AB15 ADC1_AIN3 ADC1_AIN3 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AA15 ADC1_AIN4 ADC1_AIN4 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
Y15 ADC1_AIN5 ADC1_AIN5 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AE16 ADC1_AIN6 ADC1_AIN6 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AD16 ADC1_AIN7 ADC1_AIN7 0x0 A Z Z Mode0 VDDA_ADC1 NA 25 NA Analog
AC18 cam0_field spi2_sclk 0x4 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
EMU4 0x6 IO
gpio4_2 0x7 IO
AE17 cam0_hd pr1_edio_sof 0x3 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi2_cs1 0x4 IO
EMU10 0x5 IO
EMU2 0x6 IO
gpio4_0 0x7 IO
AC20 cam0_pclk pr0_pru0_gpo14 0x3 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi2_cs0 0x4 IO
pr0_pru0_gpi14 0x5 I
EMU6 0x6 IO
gpio4_4 0x7 IO
I2C2_SDA 0x8 IOD
AD18 cam0_vd pr1_edio_outvalid 0x3 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi2_d1 0x4 IO
EMU11 0x5 IO
EMU3 0x6 IO
gpio4_1 0x7 IO
AD17 cam0_wen spi2_d0 0x4 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
EMU5 0x6 IO
gpio4_3 0x7 IO
AC25 cam1_field xdma_event_intr7 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
ext_hw_trigger 0x2 I
spi2_cs1 0x4 IO
ehrpwm1B 0x6 O
gpio4_12 0x7 IO
ehrpwm3A 0x8 O
AD25 cam1_hd xdma_event_intr4 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi0_cs3 0x2 IO
pr0_pru1_gpo1 0x3 O
spi2_cs0 0x4 IO
pr0_pru1_gpi1 0x5 I
ehrpwm0A 0x6 O
gpio4_9 0x7 IO
AE21 cam1_pclk xdma_event_intr6 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi1_cs3 0x2 IO
pr0_pru1_gpo3 0x3 O
spi2_sclk 0x4 IO
pr0_pru1_gpi3 0x5 I
ehrpwm1A 0x6 O
gpio4_11 0x7 IO
AC23 cam1_vd xdma_event_intr5 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi1_cs2 0x2 IO
pr0_pru1_gpo2 0x3 O
spi2_cs2 0x4 IO
pr0_pru1_gpi2 0x5 I
ehrpwm0B 0x6 O
gpio4_10 0x7 IO
AB25 cam1_wen xdma_event_intr8 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
pr1_edio_sof 0x2 O
spi2_d1 0x4 IO
EMU11 0x6 IO
gpio4_13 0x7 IO
ehrpwm3B 0x8 O
AE18 cam0_data0 I2C1_SDA 0x3 IOD L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
pr0_pru1_gpo16 0x4 O
pr0_pru1_gpi16 0x5 I
ehrpwm0_synco 0x6 O
gpio5_19 0x7 IO
AB18 cam0_data1 I2C1_SCL 0x3 IOD L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
pr0_pru1_gpo17 0x4 O
pr0_pru1_gpi17 0x5 I
ehrpwm3_synco 0x6 O
gpio5_20 0x7 IO
Y18 cam0_data2 mmc1_clk 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
qspi_clk 0x3 IO
gpio4_24 0x7 IO
AA18 cam0_data3 mmc1_cmd 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
qspi_csn 0x3 O
gpio4_25 0x7 IO
AE19 cam0_data4 mmc1_dat0 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
qspi_d0 0x3 IO
ehrpwm3A 0x6 O
gpio4_26 0x7 IO
AD19 cam0_data5 mmc1_dat1 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
qspi_d1 0x3 I
ehrpwm3B 0x6 O
gpio4_27 0x7 IO
AE20 cam0_data6 mmc1_dat2 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
qspi_d2 0x3 I
ehrpwm1A 0x6 O
gpio4_28 0x7 IO
AD20 cam0_data7 mmc1_dat3 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
qspi_d3 0x3 I
ehrpwm1B 0x6 O
gpio4_29 0x7 IO
AB19 cam0_data8 pr0_pru0_gpo15 0x3 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi2_cs2 0x4 IO
pr0_pru0_gpi15 0x5 I
EMU7 0x6 IO
gpio4_5 0x7 IO
I2C2_SCL 0x8 IOD
AA19 cam0_data9 pr0_pru0_gpo16 0x3 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi2_cs3 0x4 IO
pr0_pru0_gpi16 0x5 I
EMU8 0x6 IO
gpio4_6 0x7 IO
AB20 cam1_data0 uart1_rxd 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi3_d0 0x2 IO
I2C2_SDA 0x3 IOD
ehrpwm0_tripzone_input 0x6 I
gpio4_14 0x7 IO
AC21 cam1_data1 uart1_txd 0x1 IO H H Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi3_d1 0x2 IO
I2C2_SCL 0x3 IOD
ehrpwm0_synci 0x6 I
gpio4_15 0x7 IO
AD21 cam1_data2 uart1_ctsn 0x1 IO L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi3_cs0 0x2 IO
mmc2_clk 0x3 IO
pr0_pru1_gpo10 0x4 O
pr0_pru1_gpi10 0x5 I
ehrpwm1_tripzone_input 0x6 I
gpio4_16 0x7 IO
AE22 cam1_data3 uart1_rtsn 0x1 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi3_sclk 0x2 IO
mmc2_cmd 0x3 IO
pr0_pru1_gpo11 0x4 O
pr0_pru1_gpi11 0x5 I
pr1_edc_latch0_in 0x6 I
gpio4_17 0x7 IO
AD22 cam1_data4 uart1_rin 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
uart2_rxd 0x2 IO
mmc2_dat0 0x3 IO
pr0_pru1_gpo12 0x4 O
pr0_pru1_gpi12 0x5 I
pr1_edc_latch1_in 0x6 I
gpio4_18 0x7 IO
uart0_dcdn 0x8 I
AE23 cam1_data5 uart1_dsrn 0x1 I H H Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
uart2_txd 0x2 IO
mmc2_dat1 0x3 IO
pr0_pru1_gpo13 0x4 O
pr0_pru1_gpi13 0x5 I
pr1_edio_latch_in 0x6 I
gpio4_19 0x7 IO
AD23 cam1_data6 uart1_dcdn 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
uart2_ctsn 0x2 IO
mmc2_dat2 0x3 IO
pr0_pru1_gpo14 0x4 O
pr0_pru1_gpi14 0x5 I
pr1_edio_data_in0 0x6 I
gpio4_20 0x7 IO
AE24 cam1_data7 uart1_dtrn 0x1 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
uart2_rtsn 0x2 O
mmc2_dat3 0x3 IO
pr0_pru1_gpo15 0x4 O
pr0_pru1_gpi15 0x5 I
pr1_edio_data_in1 0x6 I
gpio4_21 0x7 IO
AD24 cam1_data8 xdma_event_intr3 0x1 I L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi0_cs2 0x2 IO
pr0_pru1_gpo0 0x3 O
spi2_d0 0x4 IO
pr0_pru1_gpi0 0x5 I
EMU10 0x6 IO
gpio4_8 0x7 IO
uart0_rtsn 0x8 O
AC24 cam1_data9 pr0_pru0_gpo17 0x3 O L L Mode7 VDDSHV2 Yes 6 PU/PD LVCMOS
spi2_cs3 0x4 IO
pr0_pru0_gpi17 0x5 I
EMU9 0x6 IO
gpio4_7 0x7 IO
uart0_ctsn 0x8 I
F19 CAP_VBB_MPU CAP_VBB_MPU NA A NA NA NA NA NA NA NA NA
D6 CAP_VDDS1P8V_IOLDO CAP_VDDS1P8V_IOLDO NA POWER NA NA NA NA NA NA NA NA
AD3 CAP_VDD_RTC CAP_VDD_RTC NA A NA NA NA NA NA NA NA NA
E13 CAP_VDD_SRAM_CORE CAP_VDD_SRAM_CORE NA A NA NA NA NA NA NA NA NA
E14 CAP_VDD_SRAM_MPU CAP_VDD_SRAM_MPU NA A NA NA NA NA NA NA NA NA
H20 clkreq clkreq 0x0 O OFF H Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio0_24 0x7 IO
N1 ddr_a0 ddr_a0 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
L1 ddr_a1 ddr_a1 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
L2 ddr_a2 ddr_a2 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
P2 ddr_a3 ddr_a3 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
P1 ddr_a4 ddr_a4 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
R5 ddr_a5 ddr_a5 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
R4 ddr_a6 ddr_a6 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
R3 ddr_a7 ddr_a7 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
R2 ddr_a8 ddr_a8 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
R1 ddr_a9 ddr_a9 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
M6 ddr_a10 ddr_a10 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
T5 ddr_a11 ddr_a11 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
T4 ddr_a12 ddr_a12 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
N5 ddr_a13 ddr_a13 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
T3 ddr_a14 ddr_a14 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
T2 ddr_a15 ddr_a15 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
K1 ddr_ba0 ddr_ba0 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
K2 ddr_ba1 ddr_ba1 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
K3 ddr_ba2 ddr_ba2 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
N3 ddr_casn ddr_casn 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
M2 ddr_ck ddr_ck 0x0 O L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
M3 ddr_cke0 ddr_cke0 0x0 O L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
N6 ddr_cke1 ddr_cke1 0x0 O L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
M5 ddr_csn0 ddr_csn0 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
M4 ddr_csn1 ddr_csn1 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
E3 ddr_d0 ddr_d0 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
E2 ddr_d1 ddr_d1 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
E1 ddr_d2 ddr_d2 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
F3 ddr_d3 ddr_d3 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
G4 ddr_d4 ddr_d4 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
G3 ddr_d5 ddr_d5 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
G2 ddr_d6 ddr_d6 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
G1 ddr_d7 ddr_d7 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
H1 ddr_d8 ddr_d8 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
J6 ddr_d9 ddr_d9 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
J5 ddr_d10 ddr_d10 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
J4 ddr_d11 ddr_d11 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
J3 ddr_d12 ddr_d12 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
K6 ddr_d13 ddr_d13 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
K5 ddr_d14 ddr_d14 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
K4 ddr_d15 ddr_d15 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
V5 ddr_d16 ddr_d16 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
V4 ddr_d17 ddr_d17 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
V3 ddr_d18 ddr_d18 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
V2 ddr_d19 ddr_d19 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
V1 ddr_d20 ddr_d20 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
W4 ddr_d21 ddr_d21 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
W5 ddr_d22 ddr_d22 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
W6 ddr_d23 ddr_d23 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
Y2 ddr_d24 ddr_d24 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
Y3 ddr_d25 ddr_d25 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
Y4 ddr_d26 ddr_d26 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AA3 ddr_d27 ddr_d27 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AB2 ddr_d28 ddr_d28 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AB1 ddr_d29 ddr_d29 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AC1 ddr_d30 ddr_d30 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AC2 ddr_d31 ddr_d31 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
F4 ddr_dqm0 ddr_dqm0 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
H2 ddr_dqm1 ddr_dqm1 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
V6 ddr_dqm2 ddr_dqm2 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
Y1 ddr_dqm3 ddr_dqm3 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
F2 ddr_dqs0 ddr_dqs0 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
J2 ddr_dqs1 ddr_dqs1 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
W1 ddr_dqs2 ddr_dqs2 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AA1 ddr_dqs3 ddr_dqs3 0x0 IO L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
F1 ddr_dqsn0 ddr_dqsn0 0x0 IO H Mode0 VDDS_DDR Yes 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
J1 ddr_dqsn1 ddr_dqsn1 0x0 IO H Mode0 VDDS_DDR Yes 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
W2 ddr_dqsn2 ddr_dqsn2 0x0 IO H Mode0 VDDS_DDR Yes 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
AA2 ddr_dqsn3 ddr_dqsn3 0x0 IO H Mode0 VDDS_DDR Yes 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
M1 ddr_nck ddr_nck 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
U1 ddr_odt0 ddr_odt0 0x0 O L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
U2 ddr_odt1 ddr_odt1 0x0 O L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
N2 ddr_rasn ddr_rasn 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
T1 ddr_resetn ddr_resetn 0x0 O L Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS
T6 ddr_vref ddr_vref 0x0 AP (24) NA NA Mode0 VDDS_DDR NA NA NA Analog
AC3 ddr_vtp ddr_vtp 0x0 I (25) NA NA Mode0 VDDS_DDR NA NA NA Analog
N4 ddr_wen ddr_wen 0x0 O H Mode0 VDDS_DDR YES 8 (4) PU/PD LVCMOS/HSTL/HSUL_12
A24 dss_ac_bias_en gpmc_a11 0x1 O OFF OFF (5) Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a4 0x2 O
pr1_edio_data_in5 0x3 I
pr1_edio_data_out5 0x4 O
pr0_pru1_gpo9 0x5 O
pr0_pru1_gpi9 0x6 I
gpio2_25 0x7 IO
B22 dss_data0 (6) gpmc_a0 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_mii_mt0_clk 0x2 I
ehrpwm2A 0x3 O
pr1_pru0_gpo0 0x5 O
pr1_pru0_gpi0 0x6 I
gpio2_6 0x7 IO
A21 dss_data1 (6) gpmc_a1 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_mii0_txen 0x2 O
ehrpwm2B 0x3 O
pr1_pru0_gpo1 0x5 O
pr1_pru0_gpi1 0x6 I
gpio2_7 0x7 IO
B21 dss_data2 (6) gpmc_a2 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_mii0_txd3 0x2 O
ehrpwm2_tripzone_input 0x3 I
pr1_pru0_gpo2 0x5 O
pr1_pru0_gpi2 0x6 I
gpio2_8 0x7 IO
C21 dss_data3 (6) gpmc_a3 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_mii0_txd2 0x2 O
ehrpwm0_synco 0x3 O
pr1_pru0_gpo3 0x5 O
pr1_pru0_gpi3 0x6 I
gpio2_9 0x7 IO
A20 dss_data4 (6) gpmc_a4 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_mii0_txd1 0x2 O
eQEP2A_in 0x3 I
pr1_pru0_gpo4 0x5 O
pr1_pru0_gpi4 0x6 I
gpio2_10 0x7 IO
B20 dss_data5 (6) gpmc_a5 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_mii0_txd0 0x2 O
eQEP2B_in 0x3 I
pr1_pru0_gpo5 0x5 O
pr1_pru0_gpi5 0x6 I
gpio2_11 0x7 IO
C20 dss_data6 (6) gpmc_a6 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_edio_data_in6 0x2 I
eQEP2_index 0x3 IO
pr1_edio_data_out6 0x4 O
pr1_pru0_gpo6 0x5 O
pr1_pru0_gpi6 0x6 I
gpio2_12 0x7 IO
E19 dss_data7 (6) gpmc_a7 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
pr1_edio_data_in7 0x2 I
eQEP2_strobe 0x3 IO
pr1_edio_data_out7 0x4 O
pr1_pru0_gpo7 0x5 O
pr1_pru0_gpi7 0x6 I
gpio2_13 0x7 IO
A19 dss_data8 (6) gpmc_a12 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm1_tripzone_input 0x2 I
mcasp0_aclkx 0x3 IO
uart5_txd 0x4 O
pr1_mii0_rxd3 0x5 I
uart2_ctsn 0x6 IO
gpio2_14 0x7 IO
B19 dss_data9 (6) gpmc_a13 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm0_synco 0x2 O
mcasp0_fsx 0x3 IO
uart5_rxd 0x4 I
pr1_mii0_rxd2 0x5 I
uart2_rtsn 0x6 O
gpio2_15 0x7 IO
A18 dss_data10 (6) gpmc_a14 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm1A 0x2 O
mcasp0_axr0 0x3 IO
pr1_mii0_rxd1 0x5 I
uart3_ctsn 0x6 IO
gpio2_16 0x7 IO
B18 dss_data11 (6) gpmc_a15 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
ehrpwm1B 0x2 O
mcasp0_ahclkr 0x3 IO
mcasp0_axr2 0x4 IO
pr1_mii0_rxd0 0x5 I
uart3_rtsn 0x6 O
gpio2_17 0x7 IO
spi3_cs1 0x8 IO
C19 dss_data12 (6) gpmc_a16 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP1A_in 0x2 I
mcasp0_aclkr 0x3 IO
mcasp0_axr2 0x4 IO
pr1_mii0_rxlink 0x5 I
uart4_ctsn 0x6 I
gpio0_8 0x7 IO
spi3_sclk 0x8 IO
D19 dss_data13 (6) gpmc_a17 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP1B_in 0x2 I
mcasp0_fsr 0x3 IO
mcasp0_axr3 0x4 IO
pr1_mii0_rxer 0x5 I
uart4_rtsn 0x6 O
gpio0_9 0x7 IO
spi3_d0 0x8 IO
C17 dss_data14 (6) gpmc_a18 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP1_index 0x2 IO
mcasp0_axr1 0x3 IO
uart5_rxd 0x4 I
pr1_mii_mr0_clk 0x5 I
uart5_ctsn 0x6 I
gpio0_10 0x7 IO
spi3_d1 0x8 IO
D17 dss_data15 (6) gpmc_a19 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
eQEP1_strobe 0x2 IO
mcasp0_ahclkx 0x3 IO
mcasp0_axr3 0x4 IO
pr1_mii0_rxdv 0x5 I
uart5_rtsn 0x6 O
gpio0_11 0x7 IO
spi3_cs0 0x8 IO
A23 dss_hsync (7) gpmc_a9 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a2 0x2 O
pr1_edio_data_in3 0x3 I
pr1_edio_data_out3 0x4 O
pr0_pru1_gpo7 0x5 O
pr0_pru1_gpi7 0x6 I
gpio2_23 0x7 IO
A22 dss_pclk gpmc_a10 0x1 O OFF L Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a3 0x2 O
pr1_edio_data_in4 0x3 I
pr1_edio_data_out4 0x4 O
pr0_pru1_gpo8 0x5 O
pr0_pru1_gpi8 0x6 I
gpio2_24 0x7 IO
B23 dss_vsync (8) gpmc_a8 0x1 O OFF OFF Mode7 VDDSHV6 Yes 6 PU/PD LVCMOS
gpmc_a1 0x2 O
pr1_edio_data_in2 0x3 I
pr1_edio_data_out2 0x4 O
pr0_pru1_gpo6 0x5 O
pr0_pru1_gpi6 0x6 I
gpio2_22 0x7 IO
G24 eCAP0_in_PWM0_out eCAP0_in_PWM0_out 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
uart3_txd 0x1 IO
spi1_cs1 0x2 IO
pr1_ecap0_ecap_capin_apwm_o 0x3 IO
spi1_sclk 0x4 IO
mmc0_sdwp 0x5 I
xdma_event_intr2 0x6 I
gpio0_7 0x7 IO
ehrpwm2B 0x8 O
timer1 0x9 IO
N23 EMU0 EMU0 0x0 IO H H Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio3_7 0x7 IO
T24 EMU1 EMU1 0x0 IO H H Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio3_8 0x7 IO
G25 EXTINTn nNMI 0x0 I OFF H Mode0 VDDSHV3 Yes NA PU/PD LVCMOS
D25 gpio5_8 pr1_mii0_col 0x5 I OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio5_8 0x7 IO
F24 gpio5_9 pr1_mii1_col 0x5 I OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio5_9 0x7 IO
G20 gpio5_10 I2C1_SCL 0x1 IOD OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
pr1_mii0_crs 0x5 I
gpio5_10 0x7 IO
F23 gpio5_11 pr1_mii1_crs 0x5 I OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio5_11 0x7 IO
E25 gpio5_12 I2C1_SDA 0x1 IOD OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
pr1_mii0_rxlink 0x5 I
gpio5_12 0x7 IO
E24 gpio5_13 pr1_mii1_rxlink 0x5 I OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio5_13 0x7 IO
C3 gpmc_a0 gpmc_a0 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_a16 0x4 O
pr1_mii1_txen 0x5 O
ehrpwm1_tripzone_input 0x6 I
gpio1_16 0x7 IO
C5 gpmc_a1 gpmc_a1 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat0 0x3 IO
gpmc_a17 0x4 O
pr1_mii1_rxdv 0x5 I
ehrpwm0_synco 0x6 O
gpio1_17 0x7 IO
C6 gpmc_a2 gpmc_a2 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat1 0x3 IO
gpmc_a18 0x4 O
pr1_mii1_txd3 0x5 O
ehrpwm1A 0x6 O
gpio1_18 0x7 IO
A4 gpmc_a3 gpmc_a3 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat2 0x3 IO
gpmc_a19 0x4 O
pr1_mii1_txd2 0x5 O
ehrpwm1B 0x6 O
gpio1_19 0x7 IO
D7 gpmc_a4 gpmc_a4 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_a20 0x4 O
pr1_mii1_txd1 0x5 O
eQEP1A_in 0x6 I
gpio1_20 0x7 IO
E7 gpmc_a5 gpmc_a5 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_a21 0x4 O
pr1_mii1_txd0 0x5 O
eQEP1B_in 0x6 I
gpio1_21 0x7 IO
E8 gpmc_a6 gpmc_a6 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat4 0x3 IO
gpmc_a22 0x4 O
pr1_mii_mt1_clk 0x5 I
eQEP1_index 0x6 IO
gpio1_22 0x7 IO
F6 gpmc_a7 gpmc_a7 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat5 0x3 IO
gpmc_a23 0x4 O
pr1_mii_mr1_clk 0x5 I
eQEP1_strobe 0x6 IO
gpio1_23 0x7 IO
F7 gpmc_a8 gpmc_a8 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat6 0x3 IO
gpmc_a24 0x4 O
pr1_mii1_rxd3 0x5 I
mcasp0_aclkx 0x6 IO
gpio1_24 0x7 IO
B4 gpmc_a9 gpmc_a9 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
mmc2_dat7 0x3 IO
gpmc_a25 0x4 O
pr1_mii1_rxd2 0x5 I
mcasp0_fsx 0x6 IO
gpio1_25 0x7 IO
G8 gpmc_a10 gpmc_a10 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_a26 0x4 O
pr1_mii1_rxd1 0x5 I
mcasp0_axr0 0x6 IO
gpio1_26 0x7 IO
D8 gpmc_a11 gpmc_a11 0x0 O L L Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_a27 0x4 O
pr1_mii1_rxd0 0x5 I
mcasp0_axr1 0x6 IO
gpio1_27 0x7 IO
B5 gpmc_ad0 gpmc_ad0 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat0 0x1 IO
gpio1_0 0x7 IO
A5 gpmc_ad1 gpmc_ad1 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat1 0x1 IO
gpio1_1 0x7 IO
B6 gpmc_ad2 gpmc_ad2 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat2 0x1 IO
gpio1_2 0x7 IO
A6 gpmc_ad3 gpmc_ad3 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat3 0x1 IO
gpio1_3 0x7 IO
B7 gpmc_ad4 gpmc_ad4 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat4 0x1 IO
gpio1_4 0x7 IO
A7 gpmc_ad5 gpmc_ad5 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat5 0x1 IO
gpio1_5 0x7 IO
C8 gpmc_ad6 gpmc_ad6 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat6 0x1 IO
gpio1_6 0x7 IO
B8 gpmc_ad7 gpmc_ad7 0x0 IO L L Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
mmc1_dat7 0x1 IO
gpio1_7 0x7 IO
B10 gpmc_ad8 gpmc_ad8 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat0 0x2 IO
mmc2_dat4 0x3 IO
ehrpwm2A 0x4 O
pr1_mii_mt0_clk 0x5 I
spi3_sclk 0x6 IO
gpio0_22 0x7 IO
spi3_cs1 0x8 IO
gpio5_26 0x9 IO
A10 gpmc_ad9 gpmc_ad9 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat1 0x2 IO
mmc2_dat5 0x3 IO
ehrpwm2B 0x4 O
pr1_mii0_col 0x5 I
spi3_d0 0x6 IO
gpio0_23 0x7 IO
gpio5_25 0x9 IO
F11 gpmc_ad10 gpmc_ad10 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat2 0x2 IO
mmc2_dat6 0x3 IO
ehrpwm2_tripzone_input 0x4 I
pr1_mii0_txen 0x5 O
spi3_d1 0x6 IO
gpio0_26 0x7 IO
gpio5_24 0x9 IO
D11 gpmc_ad11 gpmc_ad11 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat3 0x2 IO
mmc2_dat7 0x3 IO
ehrpwm0_synco 0x4 O
pr1_mii0_txd3 0x5 O
spi3_cs0 0x6 IO
gpio0_27 0x7 IO
gpio5_23 0x9 IO
E11 gpmc_ad12 gpmc_ad12 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat4 0x2 IO
mmc2_dat0 0x3 IO
eQEP2A_in 0x4 I
pr1_mii0_txd2 0x5 O
pr1_pru0_gpi10 0x6 I
gpio1_12 0x7 IO
mcasp0_aclkx 0x8 IO
pr1_pru0_gpo10 0x9 O
C11 gpmc_ad13 gpmc_ad13 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat5 0x2 IO
mmc2_dat1 0x3 IO
eQEP2B_in 0x4 I
pr1_mii0_txd1 0x5 O
pr1_pru0_gpi11 0x6 I
gpio1_13 0x7 IO
mcasp0_fsx 0x8 IO
pr1_pru0_gpo11 0x9 O
B11 gpmc_ad14 gpmc_ad14 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat6 0x2 IO
mmc2_dat2 0x3 IO
eQEP2_index 0x4 IO
pr1_mii0_txd0 0x5 O
pr1_pru0_gpi16 0x6 I
gpio1_14 0x7 IO
mcasp0_axr0 0x8 IO
A11 gpmc_ad15 gpmc_ad15 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
mmc1_dat7 0x2 IO
mmc2_dat3 0x3 IO
eQEP2_strobe 0x4 IO
pr1_ecap0_ecap_capin_apwm_o 0x5 IO
gpio1_15 0x7 IO
mcasp0_axr1 0x8 IO
spi3_cs1 0x9 IO
A9 gpmc_advn_ale gpmc_advn_ale 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
spi0_cs3 0x1 IO
timer4 0x2 IO
qspi_d0 0x3 IO
gpio2_2 0x7 IO
C10 gpmc_be0n_cle gpmc_be0n_cle 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
spi1_cs3 0x1 IO
timer5 0x2 IO
qspi_d3 0x3 I
pr1_mii1_rxlink 0x4 I
gpmc_a5 0x5 O
spi3_cs1 0x6 IO
gpio2_5 0x7 IO
A3 gpmc_be1n gpmc_be1n 0x0 O H H Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_csn6 0x2 O
mmc2_dat3 0x3 IO
gpmc_dir 0x4 O
pr1_mii1_col 0x5 I
mcasp0_aclkr 0x6 IO
gpio1_28 0x7 IO
A12 gpmc_clk gpmc_clk 0x0 IO L L Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
gpmc_wait1 0x2 I
mmc2_clk 0x3 IO
pr1_mii1_crs 0x4 I
pr1_mdio_mdclk 0x5 O
mcasp0_fsr 0x6 IO
gpio2_1 0x7 IO
gpio0_4 0x9 IO
A8 gpmc_csn0 gpmc_csn0 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
qspi_csn 0x3 O
gpio1_29 0x7 IO
B9 gpmc_csn1 gpmc_csn1 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
gpmc_clk 0x1 IO
mmc1_clk 0x2 IO
pr1_edio_data_in6 0x3 I
pr1_edio_data_out6 0x4 O
pr1_pru0_gpo8 0x5 O
pr1_pru0_gpi8 0x6 I
gpio1_30 0x7 IO
F10 gpmc_csn2 gpmc_csn2 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
gpmc_be1n 0x1 O
mmc1_cmd 0x2 IO
pr1_edio_data_in7 0x3 I
pr1_edio_data_out7 0x4 O
pr1_pru0_gpo9 0x5 O
pr1_pru0_gpi9 0x6 I
gpio1_31 0x7 IO
B12 gpmc_csn3 gpmc_csn3 0x0 O H H Mode7 VDDSHV9 Yes 6 PU/PD LVCMOS
gpmc_wait0 0x1 I
qspi_clk 0x2 IO
mmc2_cmd 0x3 IO
pr1_mii0_crs 0x4 I
pr1_mdio_data 0x5 IO
EMU4 0x6 IO
gpio2_0 0x7 IO
E10 gpmc_oen_ren gpmc_oen_ren 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
spi0_cs2 0x1 IO
timer7 0x2 IO
qspi_d1 0x3 I
gpio2_3 0x7 IO
A2 gpmc_wait0 gpmc_wait0 0x0 I H H Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_csn4 0x2 O
mmc1_sdcd 0x4 I
pr1_mii1_crs 0x5 I
uart4_rxd 0x6 I
gpio0_30 0x7 IO
gpio5_30 0x9 IO
D10 gpmc_wen gpmc_wen 0x0 O H H Mode7 VDDSHV10 Yes 6 PU/PD LVCMOS
spi1_cs2 0x1 IO
timer6 0x2 IO
qspi_d2 0x3 I
gpio2_4 0x7 IO
B3 gpmc_wpn gpmc_wpn 0x0 O H H Mode7 VDDSHV11 Yes 6 PU/PD LVCMOS
gpmc_csn5 0x2 O
mmc2_sdcd 0x4 I
pr1_mii1_rxer 0x5 I
uart4_txd 0x6 O
gpio0_31 0x7 IO
gpio5_31 0x9 IO
Y22 I2C0_SCL I2C0_SCL 0x0 IOD OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
timer7 0x1 IO
uart2_rtsn 0x2 O
eCAP1_in_PWM1_out 0x3 IO
gpio3_6 0x7 IO
AB24 I2C0_SDA I2C0_SDA 0x0 IOD OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
timer4 0x1 IO
uart2_ctsn 0x2 IO
eCAP2_in_PWM2_out 0x3 IO
gpio3_5 0x7 IO
L23 mcasp0_aclkr mcasp0_aclkr 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
eQEP0A_in 0x1 I
mcasp0_axr2 0x2 IO
mcasp1_aclkx 0x3 IO
mmc0_sdwp 0x4 I
pr0_pru0_gpo4 0x5 O
pr0_pru0_gpi4 0x6 I
gpio3_18 0x7 IO
gpio0_18 0x9 IO
N24 mcasp0_aclkx mcasp0_aclkx 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm0A 0x1 O
spi0_cs3 0x2 IO
spi1_sclk 0x3 IO
mmc0_sdcd 0x4 I
pr0_pru0_gpo0 0x5 O
pr0_pru0_gpi0 0x6 I
gpio3_14 0x7 IO
M24 mcasp0_ahclkr mcasp0_ahclkr 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm0_synci 0x1 I
mcasp0_axr2 0x2 IO
spi1_cs0 0x3 IO
eCAP2_in_PWM2_out 0x4 IO
pr0_pru0_gpo3 0x5 O
pr0_pru0_gpi3 0x6 I
gpio3_17 0x7 IO
L24 mcasp0_ahclkx mcasp0_ahclkx 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
eQEP0_strobe 0x1 IO
mcasp0_axr3 0x2 IO
mcasp1_axr1 0x3 IO
EMU4 0x4 IO
pr0_pru0_gpo7 0x5 O
pr0_pru0_gpi7 0x6 I
gpio3_21 0x7 IO
gpio0_3 0x9 IO
K23 mcasp0_fsr mcasp0_fsr 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
eQEP0B_in 0x1 I
mcasp0_axr3 0x2 IO
mcasp1_fsx 0x3 IO
EMU2 0x4 IO
pr0_pru0_gpo5 0x5 O
pr0_pru0_gpi5 0x6 I
gpio3_19 0x7 IO
gpio0_19 0x9 IO
N22 mcasp0_fsx mcasp0_fsx 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm0B 0x1 O
spi1_cs2 0x2 IO
spi1_d0 0x3 IO
mmc1_sdcd 0x4 I
pr0_pru0_gpo1 0x5 O
pr0_pru0_gpi1 0x6 I
gpio3_15 0x7 IO
H23 mcasp0_axr0 mcasp0_axr0 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm0_tripzone_input 0x1 I
spi1_cs3 0x2 IO
spi1_d1 0x3 IO
mmc2_sdcd 0x4 I
pr0_pru0_gpo2 0x5 O
pr0_pru0_gpi2 0x6 I
gpio3_16 0x7 IO
M25 mcasp0_axr1 mcasp0_axr1 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
eQEP0_index 0x1 IO
mcasp1_axr0 0x3 IO
EMU3 0x4 IO
pr0_pru0_gpo6 0x5 O
pr0_pru0_gpi6 0x6 I
gpio3_20 0x7 IO
gpio0_2 0x9 IO
B17 mdio_clk mdio_clk 0x0 O H H Mode7 VDDSHV7 Yes 6 PU/PD LVCMOS
timer5 0x1 IO
uart5_txd 0x2 O
uart3_rtsn 0x3 O
mmc0_sdwp 0x4 I
mmc1_clk 0x5 IO
mmc2_clk 0x6 IO
gpio0_1 0x7 IO
pr1_mdio_mdclk 0x8 O
A17 mdio_data mdio_data 0x0 IO H H Mode7 VDDSHV7 Yes 6 PU/PD LVCMOS
timer6 0x1 IO
uart5_rxd 0x2 I
uart3_ctsn 0x3 IO
mmc0_sdcd 0x4 I
mmc1_cmd 0x5 IO
mmc2_cmd 0x6 IO
gpio0_0 0x7 IO
pr1_mdio_data 0x8 IO
D16 mii1_col gmii1_col 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
spi1_sclk 0x2 IO
uart5_rxd 0x3 I
mcasp1_axr2 0x4 IO
mmc2_dat3 0x5 IO
mcasp0_axr2 0x6 IO
gpio3_0 0x7 IO
gpio0_0 0x9 IO
B14 mii1_crs gmii1_crs 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_crs_dv 0x1 I
spi1_d0 0x2 IO
I2C1_SDA 0x3 IOD
mcasp1_aclkx 0x4 IO
uart5_ctsn 0x5 I
uart2_rxd 0x6 IO
gpio3_1 0x7 IO
D13 mii1_rx_clk gmii1_rxclk 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
uart2_txd 0x1 IO
rgmii1_rclk 0x2 I
mmc0_dat6 0x3 IO
mmc1_dat1 0x4 IO
uart1_dsrn 0x5 I
mcasp0_fsx 0x6 IO
gpio3_10 0x7 IO
gpio0_9 0x9 IO
A15 mii1_rx_dv gmii1_rxdv 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rgmii1_rctl 0x2 I
uart5_txd 0x3 O
mcasp1_aclkx 0x4 IO
mmc2_dat0 0x5 IO
mcasp0_aclkr 0x6 IO
gpio3_4 0x7 IO
gpio0_1 0x9 IO
B13 mii1_rx_er gmii1_rxer 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_rxer 0x1 I
spi1_d1 0x2 IO
I2C1_SCL 0x3 IOD
mcasp1_fsx 0x4 IO
uart5_rtsn 0x5 O
uart2_txd 0x6 IO
gpio3_2 0x7 IO
D14 mii1_tx_clk gmii1_txclk 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
uart2_rxd 0x1 IO
rgmii1_tclk 0x2 O
mmc0_dat7 0x3 IO
mmc1_dat0 0x4 IO
uart1_dcdn 0x5 I
mcasp0_aclkx 0x6 IO
gpio3_9 0x7 IO
gpio0_8 0x9 IO
A13 mii1_tx_en gmii1_txen 0x0 O L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_txen 0x1 O
rgmii1_tctl 0x2 O
timer4 0x3 IO
mcasp1_axr0 0x4 IO
eQEP0_index 0x5 IO
mmc2_cmd 0x6 IO
gpio3_3 0x7 IO
F17 mii1_rxd0 gmii1_rxd0 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_rxd0 0x1 I
rgmii1_rd0 0x2 I
mcasp1_ahclkx 0x3 IO
mcasp1_ahclkr 0x4 IO
mcasp1_aclkr 0x5 IO
mcasp0_axr3 0x6 IO
gpio2_21 0x7 IO
B16 mii1_rxd1 gmii1_rxd1 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_rxd1 0x1 I
rgmii1_rd1 0x2 I
mcasp1_axr3 0x3 IO
mcasp1_fsr 0x4 IO
eQEP0_strobe 0x5 IO
mmc2_clk 0x6 IO
gpio2_20 0x7 IO
E16 mii1_rxd2 gmii1_rxd2 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
uart3_txd 0x1 IO
rgmii1_rd2 0x2 I
mmc0_dat4 0x3 IO
mmc1_dat3 0x4 IO
uart1_rin 0x5 I
mcasp0_axr1 0x6 IO
gpio2_19 0x7 IO
gpio0_11 0x9 IO
C14 mii1_rxd3 gmii1_rxd3 0x0 I L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
uart3_rxd 0x1 IO
rgmii1_rd3 0x2 I
mmc0_dat5 0x3 IO
mmc1_dat2 0x4 IO
uart1_dtrn 0x5 O
mcasp0_axr0 0x6 IO
gpio2_18 0x7 IO
gpio0_10 0x9 IO
B15 mii1_txd0 gmii1_txd0 0x0 O L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_txd0 0x1 O
rgmii1_td0 0x2 O
mcasp1_axr2 0x3 IO
mcasp1_aclkr 0x4 IO
eQEP0B_in 0x5 I
mmc1_clk 0x6 IO
gpio0_28 0x7 IO
A14 mii1_txd1 gmii1_txd1 0x0 O L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
rmii1_txd1 0x1 O
rgmii1_td1 0x2 O
mcasp1_fsr 0x3 IO
mcasp1_axr1 0x4 IO
eQEP0A_in 0x5 I
mmc1_cmd 0x6 IO
gpio0_21 0x7 IO
C13 mii1_txd2 gmii1_txd2 0x0 O L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
dcan0_rx 0x1 I
rgmii1_td2 0x2 O
uart4_txd 0x3 O
mcasp1_axr0 0x4 IO
mmc2_dat2 0x5 IO
mcasp0_ahclkx 0x6 IO
gpio0_17 0x7 IO
gpio3_12 0x9 IO
C16 mii1_txd3 gmii1_txd3 0x0 O L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
dcan0_tx 0x1 O
rgmii1_td3 0x2 O
uart4_rxd 0x3 I
mcasp1_fsx 0x4 IO
mmc2_dat1 0x5 IO
mcasp0_fsr 0x6 IO
gpio0_16 0x7 IO
gpio3_11 0x9 IO
D1 mmc0_clk mmc0_clk 0x0 IO OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_a24 0x1 O
uart3_ctsn 0x2 IO
uart2_rxd 0x3 IO
dcan1_tx 0x4 O
pr0_pru0_gpo12 0x5 O
pr0_pru0_gpi12 0x6 I
gpio2_30 0x7 IO
D2 mmc0_cmd mmc0_cmd 0x0 IO OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_a25 0x1 O
uart3_rtsn 0x2 O
uart2_txd 0x3 IO
dcan1_rx 0x4 I
pr0_pru0_gpo13 0x5 O
pr0_pru0_gpi13 0x6 I
gpio2_31 0x7 IO
C1 mmc0_dat0 mmc0_dat0 0x0 IO OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_a23 0x1 O
uart5_rtsn 0x2 O
uart3_txd 0x3 IO
uart1_rin 0x4 I
pr0_pru0_gpo11 0x5 O
pr0_pru0_gpi11 0x6 I
gpio2_29 0x7 IO
C2 mmc0_dat1 mmc0_dat1 0x0 IO OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_a22 0x1 O
uart5_ctsn 0x2 I
uart3_rxd 0x3 IO
uart1_dtrn 0x4 O
pr0_pru0_gpo10 0x5 O
pr0_pru0_gpi10 0x6 I
gpio2_28 0x7 IO
B2 mmc0_dat2 mmc0_dat2 0x0 IO OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_a21 0x1 O
uart4_rtsn 0x2 O
timer6 0x3 IO
uart1_dsrn 0x4 I
pr0_pru0_gpo9 0x5 O
pr0_pru0_gpi9 0x6 I
gpio2_27 0x7 IO
B1 mmc0_dat3 mmc0_dat3 0x0 IO OFF OFF Mode7 VDDSHV1 Yes 6 PU/PD LVCMOS
gpmc_a20 0x1 O
uart4_ctsn 0x2 I
timer5 0x3 IO
uart1_dcdn 0x4 I
pr0_pru0_gpo8 0x5 O
pr0_pru0_gpi8 0x6 I
gpio2_26 0x7 IO
Y25 nTRST nTRST 0x0 I L L Mode0 VDDSHV3 Yes NA PU/PD LVCMOS
Y23 PWRONRSTn porz 0x0 I Z Z Mode0 VDDSHV3 (18) Yes NA NA LVCMOS
AA10, AA7, AA9, AB10, AB6, AB7, AB9, AC10, AC12, AC5, AC6, AC7, AC9, AD1, AD10, AD11, AD2, AD7, AE11, AE12, AE9, H19, H21, W10, Y10, Y6, Y7 Reserved Reserved (9) NA NA NA NA NA NA NA NA NA NA
A16 rmii1_ref_clk rmii1_refclk 0x0 IO L L Mode7 VDDSHV8 Yes 6 PU/PD LVCMOS
xdma_event_intr2 0x1 I
spi1_cs0 0x2 IO
uart5_txd 0x3 O
mcasp1_axr3 0x4 IO
mmc0_pow 0x5 O
mcasp1_ahclkx 0x6 IO
gpio0_29 0x7 IO
AE2 RTC_KALDO_ENn RTC_KALDO_ENn 0x0 I Z Z Mode0 VDDS_RTC NA NA NA Analog
AD6 RTC_PMIC_EN RTC_PMIC_EN 0x0 O H 1 Mode0 VDDS_RTC NA 6 NA LVCMOS
AE6 RTC_PWRONRSTn RTC_PORz 0x0 I Z Z Mode0 VDDS_RTC Yes NA NA LVCMOS
AE3 RTC_WAKEUP RTC_WAKEUP 0x0 I L Z Mode0 VDDS_RTC Yes NA NA LVCMOS
AE5 RTC_XTALIN OSC1_IN 0x0 I H H Mode0 VDDS_RTC Yes NA PU (2) LVCMOS
AE4 RTC_XTALOUT OSC1_OUT 0x0 O Z Z (29) Mode0 VDDS_RTC NA NA (19) NA LVCMOS
P23 spi0_sclk spi0_sclk 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
uart2_rxd 0x1 IO
I2C2_SDA 0x2 IOD
ehrpwm0A 0x3 O
pr1_uart0_cts_n 0x4 I
pr0_uart0_cts_n 0x5 I
EMU2 0x6 IO
gpio0_2 0x7 IO
N20 spi2_sclk spi2_sclk 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
I2C1_SCL 0x1 IOD
ehrpwm4_tripzone_input 0x6 I
gpio3_24 0x7 IO
gpio0_22 0x9 IO
P25 spi4_sclk spi4_sclk 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm0_synci 0x6 I
gpio5_4 0x7 IO
T20 spi0_cs0 spi0_cs0 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_sdwp 0x1 I
I2C1_SCL 0x2 IOD
ehrpwm0_synci 0x3 I
pr1_uart0_txd 0x4 O
pr0_uart0_txd 0x5 O
pr1_edio_data_out1 0x6 O
gpio0_5 0x7 IO
ehrpwm1B 0x8 O
R25 spi0_cs1 spi0_cs1 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
uart3_rxd 0x1 IO
eCAP1_in_PWM1_out 0x2 IO
mmc0_pow 0x3 O
xdma_event_intr2 0x4 I
mmc0_sdcd 0x5 I
EMU4 0x6 IO
gpio0_6 0x7 IO
ehrpwm2A 0x8 O
timer0 0x9 IO
T22 spi0_d0 spi0_d0 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
uart2_txd 0x1 IO
I2C2_SCL 0x2 IOD
ehrpwm0B 0x3 O
pr1_uart0_rts_n 0x4 O
pr0_uart0_rts_n 0x5 O
EMU3 0x6 IO
gpio0_3 0x7 IO
T21 spi0_d1 spi0_d1 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc1_sdwp 0x1 I
I2C1_SDA 0x2 IOD
ehrpwm0_tripzone_input 0x3 I
pr1_uart0_rxd 0x4 I
pr0_uart0_rxd 0x5 I
pr1_edio_data_out0 0x6 O
gpio0_4 0x7 IO
ehrpwm1A 0x8 O
T23 spi2_cs0 spi2_cs0 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
I2C1_SDA 0x1 IOD
ehrpwm2_tripzone_input 0x6 I
gpio3_25 0x7 IO
gpio0_23 0x9 IO
P22 spi2_d0 spi2_d0 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm5_tripzone_input 0x6 I
gpio3_22 0x7 IO
gpio0_20 0x9 IO
P20 spi2_d1 spi2_d1 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm1_tripzone_input 0x6 I
gpio3_23 0x7 IO
gpio0_21 0x9 IO
N25 spi4_cs0 spi4_cs0 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm3_tripzone_input 0x6 I
gpio5_7 0x7 IO
R24 spi4_d0 spi4_d0 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm3_synci 0x6 I
gpio5_5 0x7 IO
P24 spi4_d1 spi4_d1 0x0 IO OFF L Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
ehrpwm0_tripzone_input 0x6 I
gpio5_6 0x7 IO
AA25 TCK TCK 0x0 I H H Mode0 VDDSHV3 Yes NA PU/PD LVCMOS
Y20 TDI TDI 0x0 I H H Mode0 VDDSHV3 Yes NA PU/PD LVCMOS
AA24 TDO TDO 0x0 O H H Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
Y24 TMS TMS 0x0 I H H Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
L25 uart0_ctsn uart0_ctsn 0x0 I OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
uart4_rxd 0x1 I
dcan1_tx 0x2 O
I2C1_SDA 0x3 IOD
spi1_d0 0x4 IO
timer7 0x5 IO
pr1_edc_sync0_out 0x6 O
gpio1_8 0x7 IO
J25 uart0_rtsn uart0_rtsn 0x0 O OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
uart4_txd 0x1 O
dcan1_rx 0x2 I
I2C1_SCL 0x3 IOD
spi1_d1 0x4 IO
spi1_cs0 0x5 IO
pr1_edc_sync1_out 0x6 O
gpio1_9 0x7 IO
K25 uart0_rxd uart0_rxd 0x0 I OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
spi1_cs0 0x1 IO
dcan0_tx 0x2 O
I2C2_SDA 0x3 IOD
eCAP2_in_PWM2_out 0x4 IO
pr0_pru1_gpo4 0x5 O
pr0_pru1_gpi4 0x6 I
gpio1_10 0x7 IO
J24 uart0_txd uart0_txd 0x0 O OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
spi1_cs1 0x1 IO
dcan0_rx 0x2 I
I2C2_SCL 0x3 IOD
eCAP1_in_PWM1_out 0x4 IO
pr0_pru1_gpo5 0x5 O
pr0_pru1_gpi5 0x6 I
gpio1_11 0x7 IO
K22 uart1_ctsn uart1_ctsn 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
timer6 0x1 IO
dcan0_tx 0x2 O
I2C2_SDA 0x3 IOD
spi1_cs0 0x4 IO
pr1_uart0_cts_n 0x5 I
pr1_edc_latch0_in 0x6 I
gpio0_12 0x7 IO
L22 uart1_rtsn uart1_rtsn 0x0 O OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
timer5 0x1 IO
dcan0_rx 0x2 I
I2C2_SCL 0x3 IOD
spi1_cs1 0x4 IO
pr1_uart0_rts_n 0x5 O
pr1_edc_latch1_in 0x6 I
gpio0_13 0x7 IO
K21 uart1_rxd uart1_rxd 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc1_sdwp 0x1 I
dcan1_tx 0x2 O
I2C1_SDA 0x3 IOD
pr1_uart0_rxd 0x5 I
pr1_pru0_gpi16 0x6 I
gpio0_14 0x7 IO
L21 uart1_txd uart1_txd 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
mmc2_sdwp 0x1 I
dcan1_rx 0x2 I
I2C1_SCL 0x3 IOD
pr1_uart0_txd 0x5 O
pr1_pru0_gpi16 0x6 I
gpio0_15 0x7 IO
H22 uart3_ctsn uart3_ctsn 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
spi4_cs1 0x2 IO
pr0_pru1_gpo18 0x4 O
pr0_pru1_gpi18 0x5 I
ehrpwm5A 0x6 O
gpio5_0 0x7 IO
K24 uart3_rtsn uart3_rtsn 0x0 O OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
hdq_sio 0x1 IOD
pr0_pru1_gpo19 0x4 O
pr0_pru1_gpi19 0x5 I
ehrpwm5B 0x6 O
gpio5_1 0x7 IO
H25 uart3_rxd uart3_rxd 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
pr0_pru0_gpo18 0x4 O
pr0_pru0_gpi18 0x5 I
ehrpwm4A 0x6 O
gpio5_2 0x7 IO
H24 uart3_txd uart3_txd 0x0 IO OFF H Mode7 VDDSHV3 Yes 6 PU/PD LVCMOS
pr0_pru0_gpo19 0x4 O
pr0_pru0_gpi19 0x5 I
ehrpwm4B 0x6 O
gpio5_3 0x7 IO
W22 USB0_CE USB0_CE 0x0 A Z Z Mode0 VDDA3P3V_USB0/VDDA1P8V_USB0 NA NA NA Analog
W24 USB0_DM USB0_DM 0x0 A Z Z Mode0 VDDA3P3V_USB0/VDDA1P8V_USB0 NA (20) 8 (20) NA Analog
W25 USB0_DP USB0_DP 0x0 A Z Z Mode0 VDDA3P3V_USB0/VDDA1P8V_USB0 NA (20) 8 (20) NA Analog
G21 USB0_DRVVBUS USB0_DRVVBUS 0x0 O L L Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio0_18 0x7 IO
gpio5_27 0x9 IO
U24 USB0_ID USB0_ID 0x0 A Z Z Mode0 VDDA3P3V_USB0/VDDA1P8V_USB0 NA NA NA Analog
U23 USB0_VBUS USB0_VBUS 0x0 A Z Z Mode0 VDDA3P3V_USB0/VDDA1P8V_USB0 NA NA NA Analog
U22 USB1_CE USB1_CE 0x0 A Z Z Mode0 VDDA3P3V_USB1/VDDA1P8V_USB1 NA NA NA Analog
V25 USB1_DM USB1_DM 0x0 A Z Z Mode0 VDDA3P3V_USB1/VDDA1P8V_USB1 NA (21) 8 (21) NA Analog
V24 USB1_DP USB1_DP 0x0 A Z Z Mode0 VDDA3P3V_USB1/VDDA1P8V_USB1 NA (21) 8 (21) NA Analog
F25 USB1_DRVVBUS USB1_DRVVBUS 0x0 O L L Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
gpio3_13 0x7 IO
gpio0_25 0x9 IO
U25 USB1_ID USB1_ID 0x0 A Z Z Mode0 VDDA3P3V_USB1/VDDA1P8V_USB1 NA NA NA Analog
T25 USB1_VBUS USB1_VBUS 0x0 A Z Z Mode0 VDDA3P3V_USB1/VDDA1P8V_USB1 NA NA NA Analog
W21 VDDA1P8V_USB0 VDDA1P8V_USB0 NA POWER NA NA NA NA NA NA NA NA
U21 VDDA1P8V_USB1 VDDA1P8V_USB1 NA POWER NA NA NA NA NA NA NA NA
W20 VDDA3P3V_USB0 VDDA3P3V_USB0 NA POWER NA NA NA NA NA NA NA NA
U20 VDDA3P3V_USB1 VDDA3P3V_USB1 NA POWER NA NA NA NA NA NA NA NA
AB12 VDDA_ADC0 VDDA_ADC0 NA POWER NA NA NA NA NA NA NA NA
Y16 VDDA_ADC1 VDDA_ADC1 NA POWER NA NA NA NA NA NA NA NA
AD12, AD8, F20, G6, H12, P19, W15, Y19 VDDS VDDS (1) NA POWER NA NA NA NA NA NA NA NA
F8 VDDS3P3V_IOLDO VDDS3P3V_IOLDO NA POWER NA NA NA NA NA NA NA NA
J7, J8 VDDSHV1 VDDSHV1 NA POWER NA NA NA NA NA NA NA NA
V16, V17, W16 VDDSHV2 VDDSHV2 NA POWER NA NA NA NA NA NA NA NA
J18, K17, K18, N18, N19, P18, W18 VDDSHV3 VDDSHV3 NA POWER NA NA NA NA NA NA NA NA
F22 VDDSHV5 VDDSHV5 NA POWER NA NA NA NA NA NA NA NA
G16, G17, H17 VDDSHV6 VDDSHV6 NA POWER NA NA NA NA NA NA NA NA
F16 VDDSHV7 VDDSHV7 NA POWER NA NA NA NA NA NA NA NA
G13, G14 VDDSHV8 VDDSHV8 NA POWER NA NA NA NA NA NA NA NA
G11, H11 VDDSHV9 VDDSHV9 NA POWER NA NA NA NA NA NA NA NA
G10, H10 VDDSHV10 VDDSHV10 NA POWER NA NA NA NA NA NA NA NA
H8, H9 VDDSHV11 VDDSHV11 NA POWER NA NA NA NA NA NA NA NA
E23 VDDS_CLKOUT VDDS_CLKOUT NA POWER NA NA NA NA NA NA NA NA
K7, K8, M7, M8, N7, N8, R6, R7, R8, T7, T8, V7, V8 VDDS_DDR VDDS_DDR NA POWER NA NA NA NA NA NA NA NA
C23 VDDS_OSC VDDS_OSC NA POWER NA NA NA NA NA NA NA NA
N21 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA POWER NA NA NA NA NA NA NA NA
G5 VDDS_PLL_DDR VDDS_PLL_DDR NA POWER NA NA NA NA NA NA NA NA
E17 VDDS_PLL_MPU VDDS_PLL_MPU NA POWER NA NA NA NA NA NA NA NA
AD5 VDDS_RTC VDDS_RTC NA POWER NA NA NA NA NA NA NA NA
F13 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA POWER NA NA NA NA NA NA NA NA
F14 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA POWER NA NA NA NA NA NA NA NA
AD9, J10, J11, L12, L14, M12, M14, M9, N16, N17, N9, P16, P17, R11, R14, R9, T11, T14, T18, T19, T9, U15, V15, W12, W13 VDD_CORE VDD_CORE (15) NA POWER NA NA NA NA NA NA NA NA
H13, H14, H16, J13, J14, J16, K19, K20, L19, L20, M17, M18 VDD_MPU VDD_MPU NA POWER NA NA NA NA NA NA NA NA
D20 vdd_mpu_mon vdd_mpu_mon (30) NA POWER NA NA NA NA NA NA NA NA
P21 VPP VPP (23) NA POWER NA NA NA NA NA NA NA NA
A1, A25, AA23, AE1, AE10, AE25, AE7, AE8, H15, H18, J12, J15, J17, J9, K11, K12, K14, K15, K9, L11, L15, L17, L18, L8, L9, M10, M11, M13, M15, M16, N10, N11, N12, N13, N14, N15, P10, P11, P12, P13, P14, P15, P8, P9, R12, R15, R17, R18, T12, T15, T17, U10, U11, U12, U13, U14, U16, U17, U18, U19, U8, U9, V10, V11, V12, V13, V14, V18, V9 VSS VSS (16) NA GROUND NA NA NA NA NA NA NA NA
AC15 VSSA_ADC VSSA_ADC NA GROUND NA NA NA NA NA NA NA NA
W23 VSSA_USB VSSA_USB NA GROUND NA NA NA NA NA NA NA NA
B24 VSS_OSC VSS_OSC (31) NA GROUND NA NA NA NA NA NA NA NA
AD4 VSS_RTC VSS_RTC (32) NA GROUND NA NA NA NA NA NA NA NA
G22 WARMRSTn nRESETIN_OUT 0x0 IOD (12) OFF H (22) Mode0 VDDSHV3 Yes 6 PU/PD LVCMOS
D24 xdma_event_intr0 xdma_event_intr0 0x0 I OFF L (10) Mode7 (13) VDDSHV5 Yes 6 PU/PD LVCMOS
ext_hw_trigger 0x1 I
timer4 0x2 IO
clkout1 0x3 O
spi1_cs1 0x4 IO
pr1_pru0_gpi16 0x5 I
EMU2 0x6 IO
gpio0_19 0x7 IO
pr1_mdio_data 0x8 IO
gpio5_28 0x9 IO
C24 xdma_event_intr1 xdma_event_intr1 0x0 I OFF L (11) Mode7 (14) VDDSHV5 Yes 6 PU/PD LVCMOS
spi0_cs2 0x1 IO
tclkin 0x2 I
clkout2 0x3 O
timer7 0x4 IO
pr1_pru0_gpi16 0x5 I
EMU3 0x6 IO
gpio0_20 0x7 IO
pr1_mdio_mdclk 0x8 O
gpio5_29 0x9 IO
C25 XTALIN OSC0_IN 0x0 (3) I Z Z Mode0 VDDS_OSC Yes NA PD LVCMOS
B25 XTALOUT OSC0_OUT 0x0 O Z Z Mode0 VDDS_OSC NA NA (19) NA LVCMOS
  1. AD12 and AD8 are not connected to VDDS in the device, but they are required to be connected to 1.8V VDDS on the board
  2. An internal 10 kohm pull up is turned on when the oscillator is disabled. The oscillator is disabled by default after power is applied.
  3. An internal 15 kohm pull down is turned on when the oscillator is disabled. The oscillator is enabled by default after power is applied.
  4. Buffer strength of 8mA is for 50ohms. Can be programmed to have a drive of 5-12mA. See TRM (Control Module) for details.
  5. DSS_AC_BIAS_EN terminal is SYSBOOT[18] input, latched on the rising edge of PWRONRSTn
  6. DSS_DATA[15:0] terminals are respectively SYSBOOT[15:0] inputs, latched on the rising edge of PWRONRSTn.
  7. DSS_HSYNC terminal is SYSBOOT[17] input, latched on the rising edge of PWRONRSTn.
  8. DSS_VSYNC terminal is SYSBOOT[16] input, latched on the rising edge of PWRONRSTn.
  9. Do not connect any signal, test point, or board trace to reserved signals.
  10. If sysboot[17] is low on the rising edge of PWRONRSTn, this terminal has an internal pull-down turned on after reset is released. If sysboot[17] is high on the rising edge or PWRONRSTn, this terminal will initially be driven low after reset is released then it begins to toggle at the same frequency of the OSC0_IN terminal.
  11. If sysboot[18] is low on the rising edge of PWRONRSTn, this terminal has an internal pull-down turned on after reset is released. If sysboot[18] is high on the rising edge or PWRONRSTn, this terminal will initially be driven low after reset is released then it begins to toggle at either 25MHz or 50MHz, depending on the value of SYSBOOT[5].
  12. Refer to the External Warm Reset section of the Technical Reference Manual for more information related to the operation of this terminal.
  13. Reset Release Mode = 7 if sysboot[17] is low. Mode = 3 if sysboot[17] is high.
  14. Reset Release Mode = 7 if sysboot[18] is low. Mode = 3 if sysboot[18] is high.
  15. Terminal AD9 is not connected to VDD_CORE in the device, but it is required to be connected to VDD_CORE on the board
  16. Terminals AA23, AE10, AE7, AE8 are not connected to VSS in the device, but they are required to be connected to board ground
  17. The default Pull controls for after reset are set by Control Module Registers (DDR IO Ctrl). Please refer to TRM (Control Module) for details.
  18. The input voltage thresholds for this input are not a function of VDDSHV3. Please refer to the DC Electrical Characteristics section for details related to electrical parameters associated with this input terminal
  19. This output should only be used to source the recommended crystal circuit.
  20. This parameter only applies when this USB PHY terminal is operating in UART2 mode.
  21. This parameter only applies when this USB PHY terminal is operating in UART3 mode.
  22. This pin is configured as Open-drain and hence is expected to have an external Pull-up resistor. However there is also an internal PU resistor by default enabled after reset is deasserted.
  23. This signal is only valid for High Security (AM437xHS) devices. For more details, please refer to the VPP Specification for One-Time Programmable (OTP) eFUSEs section. This signal is reserved for AM437x devices, and thus do not connect any signal, test point, or board trace to this signal for AM437x devices
  24. This terminal is an analog input used to set the switching threshold of the DDR input buffers to (VDDS_DDR / 2).
  25. This terminal is an analog passive signal that connects to an external 49.9 ohm 1%, 20mW reference resistor which is used to calibrate the DDR input/output buffers.
  26. This terminal is analog input that may also be configured as an open-drain output.
  27. This terminal is analog input that may also be configured as an open-source or open-drain output.
  28. This terminal is analog input that may also be configured as an open-source output.
  29. This terminal is high-Z when the oscillator is disabled. This terminal is driven high if RTC_XTALIN is less than VIL, driven low if RTC_XTALIN is greater than VIH, and driven to a unknown value if RTC_XTALIN is between VIL and VIH when the oscillator is enabled. The oscillator is disabled by default after power is applied.
  30. This terminal provides a Kelvin connection to VDD_MPU. It can be connected to the power supply feedback input to provide remote sensing which compensates for voltage drop in the PCB power distribution network and package. When the Kelvin connection is not used it should be connected to the same power source as VDD_MPU.
  31. This terminal provides a Kelvin ground reference for the external crystal components. If a crystal circuit is connected to the OSC0_IN/OSC0_OUT terminals, the crystal circuit component grounds should be connected to this terminal and also be connected to the PCB ground plane close to this terminal. If an external LVCMOS clock source is connected to the OSC0_IN terminal, this terminal should be connected to VSS.
  32. This terminal provides a Kelvin ground reference for the external crystal components. If a crystal circuit is connected to the OSC1_IN/OSC1_OUT terminals, the crystal circuit component grounds should be connected to this terminal and also should be connected to the PCB ground plane close to this terminal. If an external LVCMOS clock source is connected to the OSC1_IN terminal, this terminal should be connected to VSS
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