4 Revision History

Changes from Revision A (May 2021) to Revision B (July 2023)

• Corrected common drain to common source in ACDRVx pin function in Section 6 Go
• Clarified /QON pull up voltage in Section 6 Go
• Deleted SDRV connected to BAT when shipFET disabled as an option in Section 6 Go
• Updated: V_{SYSMIN_REG_ACC} Go
• Updated V_{OTG_ACC} Go
• Changed Functional Block DiagramGo
• Corrected default charge current to 1 A in Section 8.3.2 Go
• Clarified PFM peak inductor current in Section 8.3.6.4 Go
• Added charge current clamp during SYSMIN operation in Section 8.3.9.2 Go
• Clarified trickle to precharge regulation in Section 8.3.9.2 Go
• Added SDRV typical output voltage and current to Section 8.3.12 Go
• Updated I2C terminology in text and figures in Section 8.3.14 Go
• Corrected REG0x03 default charge current to 1A and max charge current to 3 A in Section 8.5.1 Go
• Changed REG0x09 bit5 from RESERVED to STOP_WD_CHG in Section 8.5.1 Go
• Added REG0x10 bits5-4 in Section 8.5.1 Go
• Clarified REG0x14 and REG0x33 regarding reporting IBAT discharge current in Section 8.5.1 Go
• Changed REG0x2E to no longer recommend 12-bit ADC setting in Section 8.5.1 Go
• Changed REG0x2E to Running average (not available for IBAT discharge) in Section 8.5.1 Go
• Corrected PN and DEV_REV naming in REG0x48 in Section 8.5.1 Go
• Added optional input snubber/TVS to application diagrams in Section 9.2 Go