5 Pin Configuration and Functions

BQ25856-Q1 BQ25856-Q1, RRV Package36-Pin VQFNTop
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Figure 5-1 BQ25856-Q1, RRV Package36-Pin VQFNTop View

Table 5-1 Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
SCL	1	I	I²C Interface Clock – Connect SCL to the logic rail through a 10-kΩ resistor.
SDA	2	IO	I²C Interface Data – Connect SDA to the logic rail through a 10-kΩ resistor.
INT	3	O	Open Drain Interrupt Output – Connect the INT pin to a logic rail via 10-kΩ resistor. The INT pin sends an active low, 256-μs pulse to host to report the charger device status and faults.
STAT1	4	O	Open Drain Charge Status 1 Output – STAT1 and STAT2 indicate various charger operations, see Table 7-6. Connect to the pull up rail via 10-kΩ resistor. The STAT1, STAT2 pin functions can be disabled when DIS_STAT_PINS bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT1_ON bit.
STAT2	5	O	Open Drain Charge Status 2 Output – STAT1 and STAT2 indicate various charger operations, see Table 7-6. Connect to the pull up rail via 10-kΩ resistor. The STAT1, STAT2 pin functions can be disabled when DIS_STAT_PINS bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT2_ON bit.
PG	6	O	Open Drain Active Low Power Good Indicator – Connect to the pull up rail via 10-kΩ resistor. LOW indicates a good input source if VAC is within the programmed ACUV / ACOV operating window. The PG pin function can be disabled when DIS_PG_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT3_ON bit.
CE	7	IO	Active Low Charge Enable Pin – Battery charging is enabled when EN_CHG bit is 1 and CE pin is LOW. CE pin must be pulled HIGH or LOW, do not leave floating. The CE pin function can be disabled when DIS_CE_PIN bit is set to 1. When disabled, this pin can be used as a general purpose indicator via the FORCE_STAT4_ON bit.
TS	8	I	Temperature Qualification Voltage Input – Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS to PGND. Charge suspends when TS pin voltage is out of range. Recommend 103AT-2 10-kΩ thermistor.
ICHG	9	I	Charge Current Limit Setting – ICHG pin sets the maximum charge current, and can be used to monitor the charge current. A programming resistor to PGND is used to set the charge current limit as I_CHG = K_ICHG / R_ICHG. When the device is under charge current regulation, the voltage at ICHG pin is V_{REF_ICHG}. When ICHG pin voltage is less than V_{REF_ICHG}, the actual charge current can be calculated as: IBAT = K_ICHG x V_ICHG / ( R_ICHG x V_{REF_ICHG}). The actual charge current limit is the lower of the limits set by ICHG pin or the ICHG_REG register bits. This pin function can be disabled when EN_ICHG_PIN bit is 0. If ICHG pin is not used, this pin should be pulled to PGND, do not leave floating.
ILIM_HIZ	10	I	Input Current Limit Setting and HIZ Mode Control Pin – ILIM_HIZ pin sets the maximum input current limit, can be used to monitor the input current and can be pulled HIGH to force device into HIZ mode. A programming resistor to PGND is used to set the input current limit as I_LIM = K_ILIM / R_ILIM. When the device is under input current regulation, the voltage at ILIM_HIZ pin is V_{REF_ILIM}. When ILIM_HIZ pin voltage is less than V_{REF_ILIM}, the actual input current can be calculated as: IAC = K_ILIM x V_ILIM / ( R_ILIM x V_{REF_ILIM}). The actual input current limit is the lower of the limits set by ILIM_HIZ pin or the IAC_DPM register bits. This pin function can be disabled when EN_ILIM_HIZ_PIN bit is 0. If ILIM_HIZ pin is not used, this pin should be pulled to PGND, do not leave floating.
FBG	11	I	Voltage Feedback Divider Return – Connect to the bottom of battery feedback resistor. When charging, this pin is driven to PGND internally. When input voltage is outside of the ACUV / ACOV operating window, this pin is high-impedance, minimizing battery leakage current.
FB	12	I	Charge Voltage Analog Feedback Adjustment – Connect the output of a resistive voltage divider from the battery terminals to this node to adjust the output battery regulation voltage.
SRN	13	I	Charge Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to PGND for common-mode filtering.
SRP	14	I	Charge Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to PGND for common-mode filtering.
NC	15	-	No Connect - Leave this pin floating, do not tie to PGND
NC	16	-	No Connect - Leave this pin floating, do not tie to PGND
PGND	17	-	Tie this pin directly to PGND.
SW2	18	P	Boost Side Half Bridge Switching Node – Connect to the source of boost HS FET and the drain of boost LS FET. Connect the inductor between SW1 and SW2.
HIDRV2	19	O	Boost Side High-Side Gate Driver – Connect to the boost high-side N-channel MOSFET gate.
BTST2	20	P	Boost Side High-Side Power MOSFET Gate Driver Power Supply – Connect a 100nF capacitor between BTST2 and SW2 to provide bias to the high-side MOSFET gate driver.
LODRV2	21	O	Boost Side Low-Side Gate Driver – Connect to the boost low-side N-channel MOSFET gate.
PGND	22	P	Power Ground Return – The high current ground connection for the low-side gate drivers.
DRV_SUP	23	P	Charger Gate Drive Supply Input – Voltage on this pin is used to drive the gates of buck-boost converter switching FET. Connect a 4.7-μF ceramic capacitor from DRV_SUP to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 7.3.3.2 for more details.
REGN	24	P	Charger Internal Linear Regulator Output – Connect a 4.7-μF ceramic capacitor from REGN to power ground. REGN LDO voltage can be used as the gate driver supply for all switching FETs by connecting REGN to DRV_SUP pin. In high-voltage applications, it is possible to directly provide the DRV_SUP voltage with an external supply up to 12 V to achieve higher switching efficiency. See Section 7.3.3.2 for more details.
LODRV1	25	O	Buck Side Low-Side Gate Driver – Connect to the buck low-side N-channel MOSFET gate.
BTST1	26	P	Buck Side High-Side Power MOSFET Gate Driver Power Supply – Connect a 100nF capacitor between BTST1 and SW1 to provide bias to the high-side MOSFET gate driver.
HIDRV1	27	O	Buck Side High-Side Gate Driver – Connect to the buck high-side N-channel MOSFET gate.
SW1	28	P	Buck Side Half Bridge Switching Node – Connect to the source of buck HS FET and the drain of buck LS FET. Connect the inductor between SW1 and SW2.
ACN	29	I	Adapter Current-Sense Resistor, Negative Input – A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to PGND for common-mode filtering.
ACP	30	I	Adapter Current-Sense Resistor, Positive Input – A 0.47-μF ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to PGND for common-mode filtering
NC	31	-	No Connect - Leave this pin floating, do not tie to PGND
VAC	32	P	Input Voltage Detection and Power – Connect a 1-µF capacitor from pin to PGND. Pin 33 is the input bias to power the IC, and ACOV/ACUV resistor divider should be connected relative to pin 33. When Reverse Mode is enabled, pin 32 is regulated to VAC_REV.
VAC	33	P
ACUV	34	I	AC Undervoltage Comparator Input – Connect a resistor divider from VAC to PGND to program the undervoltage protection. When this pin falls below V_{REF_ACUV}, the device stops charging. The hardware limit for input voltage regulation reference is V_{ACUV_DPM}. The actual input voltage regulation is the higher of the pin-programmed value and the VAC_DPM register value. If ACUV programming is not used, pull this pin to VAC, do not leave floating.
ACOV	35	I	AC Overvoltage Comparator Input – Connect a resistor divider from VAC to PGND to program the overvoltage protection. When this pin rises above V_{REF_ACOV}, the device stops charging. If ACOV programming is not used, pull this pin to PGND, do not leave floating.
FSW_SYNC	36	I	Switching Frequency and Synchronization Input – An external resistor is connected to the FSW_SYNC pin and PGND to set the nominal switching frequency. This pin can also be used to synchronize the PWM controller to an external clock with 200-kHz to 600-kHz frequency.
Thermal Pad	37	P	Exposed pad beneath the IC – Always solder the thermal pad to the board, and have vias on the thermal pad plane star-connecting to PGND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.