ZHCSHR0B September 2017 – September 2019 BQ25910
PRODUCTION DATA.
Table 3 lists the memory-mapped registers for the I2C. All register offset addresses not listed in Table 3 should be considered as reserved locations and the register contents should not be modified.
| Address | Access Type | Acronym | Register Name | Section |
|---|---|---|---|---|
| 0h | R/W | REG00 | Battery Voltage Limit | Go |
| 1h | R/W | REG01 | Charge Current Limit | Go |
| 2h | R/W | REG02 | Input Voltage Limit | Go |
| 3h | R/W | REG03 | Input Current Limit | Go |
| 4h | R/W | REG04 | RESERVED | Go |
| 5h | R/W | REG05 | Charger Control 1 | Go |
| 6h | R/W | REG06 | Charger Control 2 | Go |
| 7h | R | REG07 | INT Status | Go |
| 8h | R | REG08 | FAULT Status | Go |
| 9h | R | REG09 | INT Flag | Go |
| Ah | R | REG0A | FAULT Flag | Go |
| Bh | R/W | REG0h | INT Mask | Go |
| Ch | R/W | REG0C | FAULT Mask | Go |
| Dh | R/W | REG0D | Part Information | Go |
Complex bit access types are encoded to fit into small table cells. Table 4 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset Value | ||
| -n | Value after reset | |
| -X | Undefined value | |