ZHCSHR0B September   2017  – September 2019 BQ25910

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Device Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery without Input Source
      3. 7.3.3  Device Power Up from Input Source
      4. 7.3.4  Power Up REGN LDO
      5. 7.3.5  Poor Source Qualification
      6. 7.3.6  Converter Power-Up
      7. 7.3.7  Three-Level Buck Converter Theory of Operation
      8. 7.3.8  Host Mode and Default Mode
        1. 7.3.8.1 Host Mode and Default Mode in BQ25910
      9. 7.3.9  Battery Charging Management
        1. 7.3.9.1 Autonomous Charging Cycle
      10. 7.3.10 Master Charger and Parallel Charger Interactions
      11. 7.3.11 Battery Charging Profile
        1. 7.3.11.1 Charging Termination
        2. 7.3.11.2 Differential Battery Voltage Remote Sensing
        3. 7.3.11.3 Charging Safety Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1 Lossless Current Sensing
      2. 7.4.2 Dynamic Power Management
      3. 7.4.3 Interrupt to Host (INT)
      4. 7.4.4 Protections
        1. 7.4.4.1 Voltage and Current Monitoring
          1. 7.4.4.1.1 Input Over-Voltage (VVBUS_OV)
          2. 7.4.4.1.2 Input Under-Voltage (VPOORSRC)
          3. 7.4.4.1.3 Flying Capacitor Over- or Under-Voltage Protection (VCFLY_OVP and VCFLY_UVP)
          4. 7.4.4.1.4 Over Current Protection
        2. 7.4.4.2 Thermal Regulation and Thermal Shutdown
        3. 7.4.4.3 Battery Protection
          1. 7.4.4.3.1 Battery Over-Voltage Protection (BATOVP)
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Data Validity
      3. 7.5.3 START and STOP Conditions
      4. 7.5.4 Byte Format
      5. 7.5.5 Acknowledge (ACK) and Not Acknowledge (NACK)
      6. 7.5.6 Slave Address and Data Direction Bit
      7. 7.5.7 Single Read and Write
      8. 7.5.8 Multi-Read and Multi-Write
    6. 7.6 Register Maps
      1. 7.6.1 I2C Registers
        1. 7.6.1.1  Battery Voltage Regulation Limit Register (Address = 0h) [reset = AAh]
          1. Table 5. REG00 Register Field Descriptions
        2. 7.6.1.2  Charger Current Limit Register (Address = 1h) [reset = 46h]
          1. Table 6. REG01 Register Field Descriptions
        3. 7.6.1.3  Input Voltage Limit Register (Address = 2h) [reset = 04h]
          1. Table 7. REG02 Register Field Descriptions
        4. 7.6.1.4  Input Current Limit Register (Address = 3h) [reset = 13h]
          1. Table 8. REG03 Register Field Descriptions
        5. 7.6.1.5  Reserved Register (Address = 4h) [reset = 03h]
          1. Table 9. REG04 Register Field Descriptions
        6. 7.6.1.6  Charger Control 1 Register (Address = 5h) [reset = 9Dh]
          1. Table 10. REG05 Register Field Descriptions
        7. 7.6.1.7  Charger Control 2 Register (Address = 6h) [reset = 33h]
          1. Table 11. REG06 Register Field Descriptions
        8. 7.6.1.8  INT Status Register (Address = 7h) [reset = X]
          1. Table 12. REG07 Register Field Descriptions
        9. 7.6.1.9  FAULT Status Register (Address = 8h) [reset = X]
          1. Table 13. REG08 Register Field Descriptions
        10. 7.6.1.10 INT Flag Status Register (Address = 9h) [reset = 00h]
          1. Table 14. REG09 Register Field Descriptions
        11. 7.6.1.11 FAULT Flag Register (Address = Ah) [reset = 00h]
          1. Table 15. REG0A Register Field Descriptions
        12. 7.6.1.12 INT Mask Register (Address = Bh) [reset = 00h]
          1. Table 16. REG0h Register Field Descriptions
        13. 7.6.1.13 FAULT Mask Register (Address = Ch) [reset = 00h]
          1. Table 17. REG0C Register Field Descriptions
        14. 7.6.1.14 Part Information Register (Address = Dh) [reset = 0Ah]
          1. Table 18. REG0D Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Passive Recommendation
        2. 8.2.2.2 Inductor Selection
        3. 8.2.2.3 Input Capacitor
        4. 8.2.2.4 Flying Capacitor
        5. 8.2.2.5 Output Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
        1. 11.1.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • YFF|36
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.1.9 FAULT Status Register (Address = 8h) [reset = X]

REG08 is shown in Figure 39 and described in Table 13.

Return to Summary Table.

When the watchdog timer expires (WD_STAT = 1h), the VBUS_OVP_STAT, TSHUT_STAT, BATOVP_STAT, and CFLY_STAT bits are held in reset until the watchdog fault is cleared (WD_RST bit = 1h, or changing the WATCHDOG[1:0] bits).

Figure 39. REG08 Register
7 6 5 4 3 2 1 0
VBUS_OVP_STAT TSHUT_STAT BATOVP_STAT CFLY_STAT RESERVED CAP_COND_STAT POORSRC_STAT RESERVED
R-X R-X R-X R-X R-0h R-X R-X R-0h

Table 13. REG08 Register Field Descriptions

Bit Field Type Reset by REG_RST Reset by WATCHDOG Description
7 VBUS_OVP_STAT R Yes Yes

Input-overvoltage status

0h = Normal

1h = Device in overvoltage protection
6 TSHUT_STAT R Yes Yes

Device temperature-shutdown status

0h = Normal

1h = Device in thermal-shutdown protection
5 BATOVP_STAT R Yes Yes

Battery overvoltage status

0h = Normal

1h = BATOVP (VBAT > VBATOVP)
4 CFLY_STAT R Yes Yes

Flying capacitor status

0h = Normal

1h = Flying capacitor fault (VCFLY_UVP or OVP)
3 Reserved R Yes Yes Reserved bit always reads 0
2 CAP_COND_STAT R Yes Yes

Capacitor precondition status

0h = Normal

1h = CFLY or CAUX precondition failed
1 POORSRC_STAT R Yes Yes

Poor-source-detection status

0h = Normal

1h = POORSRC routine failed 7 consecutive times
0 RESERVED R Yes Yes

Reserved bit always reads 0
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