8.5.2 General Purpose IOs and SPI

The BQ79606A-Q1 integrates six general purpose input/outputs (GPIOn). Registers GPIO1_CONF - GPIO6_CONF control the GPIO behavior. Each GPIO is programmable to be an input or an output. Additionally, GPIO1 - GPIO6 are configurable as ADC inputs either for NTC monitoring (ratiometric result) or absolute voltage measurement. GPIO1-GPIO6 are also configurable to be monitored by internal, hardware comparators for over/under-temperature monitoring. See Cell Over/Under-Temperature Comparatorss for more details.

The pullup and pulldowns are configurable (GPIO*_CONF[PUPD_SEL]) to be FET push-pull (between VIO and DVSS), to have an weak pullup (to VIO) or weak pulldown (to DVSS) resistor enabled. Pull-downs must not be used in output mode. Additionally, push-pull mode must not be used in input mode. If either of these configurations are selected, correct operation is not guaranteed and undesirable operation may occur.

Figure 32. Acceptable GPIO Input/Output Configurations

There is a configurable option (GPIO*_CONF[FAULT_EN]) for the GPIO to trigger a FAULT condition when high or low. When enabled, the GPIOs that are in a fault state set a flag in the GPIO_FAULT register. These faults are triggered regardless of the GPIO*_CONF[GPIO_SEL] setting for the GPIO (see the priority ranking below). Additionally, the GPIO_STAT register shows the status ('0' or '1') of the individual GPIO pins regardless of input/output configuration. While configured as an output, the state of the GPIOn is controlled using the GPIO_OUT register.

There are several functions that utilize the GPIOs as listed below. As many of these functions may mistakenly be enabled simultaneously, there is a priority to the functions. The following list shows the GPIO function priority when multiple function are simultaneously enabled (1 is the highest priority and GPIO*_CONF refers to GPIO1_CONF through GPIO6_CONF registers):

1. SPI Master enabled (SPI_CFG[SPI_EN] = 1). GPIO*_CONF[GPIO_SEL], GPIO*_CONF[FLT_EN] and GPIO*_CONF[PUPD_SEL] bits are ignored. This is only valid for GPIO3-GPIO6. GPIO1 and GPIO2 are unaffected when the SPI master is enabled.
2. GPIO Addressing enabled (GPIO*_CONF[ADD_SEL] = 1). GPIO automatically setup as input. GPIO*_CONF[GPIO_SEL], GPIO*_CONF[FLT_EN] and GPIO*_CONF[PUPD_SEL] bits are ignored. See the GPIO Addressing section for more details.
3. ADC measurements enabled (GPIO*_CONF[PUPD_SEL] = 0b000)
4. Normal GPIO behavior (GPIO*_CONF[GPIO_SEL] programmable) and GPIO configured as Fault (GPIO*_CONF[FLT_EN] is set as fault low or high)

Note that the OT/UT function is not affected by the GPIO configuration. If enabled, the OT/UT function will signal faults as normal. For example, if the SPI master is enabled and the OT/UT function is enabled on GPIOs 3-6, faults are indicated as the clock and data are driven by the master (i.e. SCLK idling low trips the OT fault on GPIO6)