SWRS037B January   2006  – March 2015 CC1150

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Attributes
  4. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  General Characteristics
    5. 4.5  Current Consumption
    6. 4.6  RF Transmit
    7. 4.7  Crystal Oscillator
    8. 4.8  Frequency Synthesizer Characteristics
    9. 4.9  Analog Temperature Sensor
    10. 4.10 DC Characteristics
    11. 4.11 Power-On Reset
    12. 4.12 Thermal Resistance Characteristics for VQFNP Package
  5. 5Detailed Description
    1. 5.1  Overview
    2. 5.2  Functional Block Diagram
    3. 5.3  Configuration Overview
    4. 5.4  Configuration Software
    5. 5.5  4-wire Serial Configuration and Data Interface
      1. 5.5.1 Chip Status Byte
      2. 5.5.2 Register Access
      3. 5.5.3 SPI Read
      4. 5.5.4 Command Strobes
      5. 5.5.5 FIFO Access
      6. 5.5.6 PATABLE Access
    6. 5.6  Microcontroller Interface and Pin Configuration
      1. 5.6.1 Configuration Interface
      2. 5.6.2 General Control and Status Pins
      3. 5.6.3 Optional Radio Control Feature
    7. 5.7  Data Rate Programming
    8. 5.8  Packet Handling Hardware Support
      1. 5.8.1 Data Whitening
      2. 5.8.2 Packet Format
        1. 5.8.2.1 Arbitrary Length Field Configuration
      3. 5.8.3 Packet Handling in Transmit Mode
      4. 5.8.4 Packet Handling in Firmware
    9. 5.9  Modulation Formats
      1. 5.9.1 Frequency Shift Keying
      2. 5.9.2 Minimum Shift Keying
      3. 5.9.3 Amplitude Modulation
    10. 5.10 Forward Error Correction with Interleaving
      1. 5.10.1 Forward Error Correction (FEC)
      2. 5.10.2 Interleaving
    11. 5.11 Radio Control
      1. 5.11.1 Power On Start-up Sequence
        1. 5.11.1.1 Automatic POR
        2. 5.11.1.2 Manual Reset
      2. 5.11.2 Crystal Control
      3. 5.11.3 Voltage Regulator Control
      4. 5.11.4 Active Mode
      5. 5.11.5 Timing
    12. 5.12 Data FIFO
    13. 5.13 Frequency Programming
    14. 5.14 VCO
      1. 5.14.1 VCO and PLL Self-Calibration
    15. 5.15 Voltage Regulators
    16. 5.16 Output Power Programming
      1. 5.16.1 Shaping and PA Ramping
    17. 5.17 General Purpose and Test Output Control Pins
    18. 5.18 Asynchronous and Synchronous Serial Operation
      1. 5.18.1 Asynchronous Serial Operation
      2. 5.18.2 Synchronous Serial Operation
    19. 5.19 System Considerations and Guidelines
      1. 5.19.1 SRD Regulations
      2. 5.19.2 Frequency Hopping and Multi-Channel Systems
      3. 5.19.3 Wideband Modulation Not Using Spread Spectrum
      4. 5.19.4 Data Burst Transmissions
      5. 5.19.5 Continuous Transmissions
      6. 5.19.6 Low-Cost Systems
      7. 5.19.7 Battery-Operated Systems
      8. 5.19.8 Increasing Output Power
    20. 5.20 Memory
      1. 5.20.1 Configuration Register Details
      2. 5.20.2 Status Register Details
  6. 6Applications, Implementation, and Layout
    1. 6.1 Application Information
      1. 6.1.1 Typical Application
    2. 6.2 Design Requirements
      1. 6.2.1 Bias Resistor
      2. 6.2.2 Balun and RF Matching
      3. 6.2.3 Crystal
      4. 6.2.4 Reference Signal
      5. 6.2.5 Additional Filtering
      6. 6.2.6 Power Supply Decoupling
    3. 6.3 PCB Layout Recommendations
      1. 6.3.1 Package Description (QLP 16)
  7. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Device Nomenclature
    2. 7.2 Documentation Support
      1. 7.2.1 Community Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Export Control Notice
    6. 7.6 Glossary
  8. 8Mechanical Packaging and Orderable Information
    1. 8.1 Packaging Information

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订购信息

4 Specifications

4.1 Absolute Maximum Ratings(1)(2)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT CONDITION
Supply voltage –0.3 3.6 V All supply pins must have the same voltage
Voltage on any digital pin –0.3 VDD + 0.3, max 3.6 V
Voltage on the pins RF_P, RF_N and DCOUPL –0.3 2.0 V
Voltage ramp-up 120 kV/µs
Input RF level +10 dBm
Storage temperature range, Tstg –50 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2) < 500 V
Charged-device model (CDM) 250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) According to JEDEC STD 22, method A114, Human Body Model

4.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT CONDITION
Operating temperature –40 85 °C
Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

4.4 General Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT CONDITION
Frequency range 300 348 MHz
400 464 MHz
800 928 MHz
Data rate 1.2 500 kBaud 2-FSK
1.2 250 kBaud GFSK, OOK and ASK
26 500 kBaud (Shaped) MSK (also known as differential offset QPSK)
Optional Manchester encoding (the data rate in kbps will be half the baud rate)

4.5 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1150EM reference design
(‎see [1] and [2]).
PARAMETER TYP UNIT CONDITION
Current consumption 200 nA Voltage regulator to digital part off, register values lost (SLEEP state)
222 µA Voltage regulator to digital part on, all other modules in power down (XOFF state)
1.1 mA Only voltage regulator to digital part and crystal oscillator running (IDLE state)
7.7 mA Only the frequency synthesizer running (FSTXON state). This current consumption also representative for the other intermediate states when going from IDLE until reaching TX, and frequency calibration states
Current consumption, 315 MHz 25.6 mA Transmit mode, +10 dBm output power (0xC4)
14.1 mA Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 ‎[3].
Current consumption, 433 MHz 26.1 mA Transmit mode, +10 dBm output power (0xC2)
14.6 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 ‎[3].
Current consumption, 868 MHz 29.3 mA Transmit mode, +10 dBm output power (0xC3)
15.5 Transmit mode, 0 dBm output power (0x60)
See more in Section 5.16 and DN012 ‎[3].
Current consumption, 915 MHz 29.3 mA Transmit mode, +10 dBm output power (0xC0)
15.2 mA Transmit mode, 0 dBm output power (0x50)
See more in Section 5.16 and DN012 ‎[3].

4.6 RF Transmit

Tc = 25°C, VDD = 3.0 V, if nothing else stated. All measurement results are obtained using the CC1150EM reference design (‎see [1] and [2]).
PARAMETER TYP MAX UNIT CONDITION
Differential load impedance 315 MHz 122 + j31 Ω Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. Follow the CC1150EM reference design (‎see [1] and [2]).
433 MHz 116 + j41 Ω
868/915 MHz 86.5 + j43 Ω
Output power, highest setting +10 dBm Output power is programmable, and full range is available across all frequency bands. Output power may be restricted by regulatory limits. See also DN006 ‎[5].
Delivered to a 50-Ω single-ended load via CC1150 EM reference design (‎see [1] and [2]) RF matching network. Maximum output power can be increased 1 to 2 dB by using wire-wound inductors instead of multilayer inductors in the balun and filter circuit for the 868/915 MHz band, see more in DN017 ‎[6].
Output power, lowest setting –30 dBm Output power is programmable, and full range is available across all frequency bands.
Delivered to a 50 Ω single-ended load via CC1150 EM reference design (‎see [1] and [2]) RF matching network.
Spurious
emissions and harmonics(1),
433/868 MHz		 25 MHz to 1 GHz –36 dBm
47 to 74 MHz,
87.5 to 118 MHz,
174 to 230 MHz,
470 to 862 MHz		 –54 dBm
Otherwise above 1 GHz –30 dBm
Spurious emissions,
315/915 MHz		 < 200 µV/m at 3 m below
960 MHz		 –49.2 dBm
EIRP
< 500 µV/m at 3 m above
960 MHz		 –41.2 dBm
EIRP
Harmonics 315 MHz 2nd, 3rd and 4th harmonic –20 dBc Whe output power is maximum
6 mV/m at 3 m (–19.6 dBm EIRP)
5th harmonic –41.2 dBm
Harmonics 915 MHz 2nd harmonic –20 dBc With +10 dBm output power
3rd, 4th, and 5th harmonic –41.2 dBm
TX latency 8 Bits Serial operation. Time from sampling the data on the transmitter data input pin until it is observed on the RF output ports.
(1) Note that close-in spurs vary with centre frequency and limits the frequencies and output power level which the CC1150 can operate at without violating regulatory restrictions. See also Section 6.2.5 for information regarding additional filtering.

4.7 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design (‎see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Crystal frequency 26 26 27 MHz
Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) aging and c) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth
Load capacitance 10 13 20 pF Simulated over operating conditions
ESR 100 Ω
Start-up time 150 µs Measured on the CC1150EM reference design (‎see [1] and [2]). This parameter is to a large degree crystal dependent.

4.8 Frequency Synthesizer Characteristics

Tc = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1150EM reference design (‎see [1] and [2]).
PARAMETER MIN TYP MAX UNIT CONDITION
Programmed frequency resolution 397 FXOSC / 216 412 Hz 26 MHz to 27 MHz crystals. The resolution (in Hz) is equal for all frequency bands.
Synthesizer frequency tolerance ±40 ppm Given by crystal used. Required accuracy (including temperature and aging) depends on frequency band and channel bandwidth / spacing.
RF carrier phase noise –82 dBc/Hz @ 50 kHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –86 dBc/Hz @ 100 kHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –90 dBc/Hz @ 200 kHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –98 dBc/Hz @ 500 kHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –106 dBc/Hz @ 1 MHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –113 dBc/Hz @ 2 MHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –119 dBc/Hz @ 5 MHz offset from carrier,
carrier at 868 MHz
RF carrier phase noise –127 dBc/Hz @ 10 MHz offset from carrier,
carrier at 868 MHz
PLL turn-on / hop time 85.1 88.4 88.4 µs Time from leaving the IDLE state until arriving in the FSTXON or TX state, when not performing calibration.
Crystal oscillator running.
PLL calibration time 18739 XOSC cycles Calibration can be initiated manually or automatically before entering or after leaving TX.
694 721 721 µs Min/typ/max time is for 27/26/26 MHz crystal frequency.

4.9 Analog Temperature Sensor(1)

Tc = 25°C, VDD = 3.0 V if nothing else is stated.
PARAMETER MIN TYP MAX UNIT CONDITION
Output voltage at –40°C 0.651 V
Output voltage at 0°C 0.747 V
Output voltage at +40°C 0.847 V
Output voltage at +80°C 0.945 V
Temperature coefficient 2.45 mV/°C Fitted from –20°C to +80°C
Absolute error in calculated temperature –2(2) 2(2) °C From –20°C to +80°C
when using
2.45 mV / °C, after 1-point calibration at room temperature
Current consumption increase when enabled 0.3 mA
(1) It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state.
(2) Indicated minimum and maximum error with 1-point calibration is based on simulated values for typical process parameters

4.10 DC Characteristics

Tc = 25°C if nothing else stated.
DIGITAL INPUTS/OUTPUTS MIN MAX UNIT CONDITION
Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD – 0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD – 0.3 VDD V For up to 4 mA output current
Logic "0" input current N/A –1 µA Input equals 0 V
Logic "1" input current N/A 1 µA Input equals VDD

4.11 Power-On Reset

For proper Power-On-Reset functionality, the power supply must comply with the requirements in this table. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 5.11.1 for a description of the recommended start-up sequence after turning power on.
PARAMETER MIN TYP MAX UNIT CONDITION
Power up ramp-up time 5 ms From 0 V until reaching 1.8 V
Power-off time 1 ms Minimum time between power on and power off

4.12 Thermal Resistance Characteristics for VQFNP Package

NAME DESCRIPTION °C/W(1)(2)
RθJC(top) Junction-to-case (top) 54.0
RθJB Junction-to-board 25.1
RθJA Junction-to-free air 48.3
PsiJT Junction-to-package top 1.6
PsiJB Junction-to-board 25.2
RθJC(bottom) Junction-to-case (bottom) 6.3
(1) °C/W = degrees Celsius per watt.
(2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:
  • JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
  • JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
Power dissipation of 2 W and an ambient temperature of 70ºC is assumed.
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