米6体育平台手机版

ZHCSFW7C december 2016 – september 2020 CC2640R2F

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RSM|32
RGZ|48
RHB|32
YFV|34

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND031W
RSM|32
- QFND112H
RHB|32
- QFND029X

订购信息

8.18 ADC Characteristics

T_c = 25°C, V_DDS = 3.0 V and voltage scaling enabled, unless otherwise noted.⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Input voltage range		0		VDDS	V
	Resolution			12		Bits
	Sample rate				200	ksps
	Offset	Internal 4.3-V equivalent reference⁽²⁾		2		LSB
	Gain error	Internal 4.3-V equivalent reference⁽²⁾		2.4		LSB
DNL⁽³⁾	Differential nonlinearity			>–1		LSB
INL⁽⁴⁾	Integral nonlinearity			±3		LSB
ENOB	Effective number of bits	Internal 4.3-V equivalent reference⁽²⁾, 200 ksps, 9.6-kHz input tone		9.8		Bits
		VDDS as reference, 200 ksps, 9.6-kHz input tone		10
		Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone		11.1
THD	Total harmonic distortion	Internal 4.3-V equivalent reference⁽²⁾, 200 ksps, 9.6-kHz input tone		–65		dB
		VDDS as reference, 200 ksps, 9.6-kHz input tone		–69
		Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone		–71
SINAD, SNDR	Signal-to-noise and Distortion ratio	Internal 4.3-V equivalent reference⁽²⁾, 200 ksps, 9.6-kHz input tone		60		dB
		VDDS as reference, 200 ksps, 9.6-kHz input tone		63
		Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone		69
SFDR	Spurious-free dynamic range	Internal 4.3-V equivalent reference⁽²⁾, 200 ksps, 9.6-kHz input tone		67		dB
		VDDS as reference, 200 ksps, 9.6-kHz input tone		68
		Internal 1.44-V reference, voltage scaling disabled, 32 samples average, 200 ksps, 300-Hz input tone		73
	Conversion time	Serial conversion, time-to-output, 24-MHz clock		50		clock-cycles
	Current consumption	Internal 4.3-V equivalent reference⁽²⁾		0.66		mA
	Current consumption	VDDS as reference		0.75		mA
	Reference voltage	Equivalent fixed internal reference (input voltage scaling enabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1.		4.3⁽²⁾⁽⁵⁾		V
	Reference voltage	Fixed internal reference (input voltage scaling disabled). For best accuracy, the ADC conversion should be initiated through the TIRTOS API in order to include the gain/offset compensation factors stored in FCFG1. This value is derived from the scaled value (4.3 V) as follows: Vref = 4.3 V × 1408 / 4095		1.48		V
	Reference voltage	VDDS as reference (Also known as RELATIVE) (input voltage scaling enabled)		VDDS		V
	Reference voltage	VDDS as reference (Also known as RELATIVE) (input voltage scaling disabled)		VDDS / 2.82⁽⁵⁾		V
	Input impedance	200 ksps, voltage scaling enabled. Capacitive input, Input impedance depends on sampling frequency and sampling time		>1		MΩ

(1) Using IEEE Std 1241™-2010 for terminology and test methods.

(2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V.

(3) No missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see Figure 8-21).

(4) For a typical example, see Figure 8-22.

(5) Applied voltage must be within absolute maximum ratings (Section 8.1) at all times.