ZHCS385D June 2013 – February 2024 CDCE913-Q1 , CDCEL913-Q1
PRODUCTION DATA
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| CLK_IN | ||||||
| fCLK | LVCMOS clock input frequency | PLL bypass mode | 0 | 160 | MHz | |
| PLL mode | 8 | 160 | ||||
| tr and tf | Rise and fall time, CLK signal (20% to 80%) | 3 | ns | |||
| Duty cycle of CLK at VDD / 2 | 40% | 60% | ||||
| I2C (SEE Figure 8-8) | ||||||
| fSCL | SCL clock frequency | Standard mode | 0 | 100 | kHz | |
| Fast mode | 0 | 400 | ||||
| tsu(START) | START setup time (SCL high before SDA low) | Standard mode | 4.7 | µs | ||
| Fast mode | 0.6 | |||||
| th(START) | START hold time (SCL low after SDA low) | Standard mode | 4 | µs | ||
| Fast mode | 0.6 | |||||
| tw(SCLL) | SCL low-pulse duration | Standard mode | 4.7 | µs | ||
| Fast mode | 1.3 | |||||
| tw(SCLH) | SCL high-pulse duration | Standard mode | 4 | µs | ||
| Fast mode | 0.6 | |||||
| th(SDA) | SDA hold time (SDA valid after SCL low) | Standard mode | 0 | 3.45 | µs | |
| Fast mode | 0 | 0.9 | ||||
| tsu(SDA) | SDA setup time | Standard mode | 250 | ns | ||
| Fast mode | 100 | |||||
| tr | SCL-SDA input rise time | Standard mode | 1000 | ns | ||
| Fast mode | 300 | |||||
| tf | SCL-SDA input fall time | 300 | ns | |||
| tsu(STOP) | STOP setup time | Standard mode | 4 | µs | ||
| Fast mode | 0.6 | |||||
| tBUS | Bus free time between a STOP and START condition | Standard mode | 4.7 | µs | ||
| Fast mode | 1.3 | |||||