9.2.1.1 Design Requirements

The CDCLVP1102 shown in Figure 20 is configured to receive a 156.25-MHz LVPECL clock from the backplane. Either signal can be then fanned out to desired devices, as shown. The configuration example is driving 2 LVPECL receivers in a line card application with the following properties:

• The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP1102 will need to be provided with 86-Ω emitter resistors near the driver for proper operation.
• The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP1102. This ASIC features internal termination so no additional components are needed.

9.2.1.2 Detailed Design Procedure

Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.

Refer to LVPECL Output Termination for output termination schemes depending on the receiver application. Unused outputs can be left floating.

In this example, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is critical for low noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on the CDCLVP1102 Evaluation Module at SCAU035.

9.2.1.3 Application Curves

The CDCLVP1102's low additive noise can be shown in this line card application. The low noise 156.25 MHz XO with 32-fs RMS jitter drives the CDCLVP1102, resulting in 57-fs RMS when integrated from 10 kHz to 20 MHz. The resultant additive jitter is a low 47-fs RMS for this configuration.

Figure 21. CDCLVP1102 Reference Phase Noise 32 fs rms (10 kHz to 20 MHz)

Figure 22. CDCLVP1102 Output Phase Noise 57 fs rms (10 kHz to 20 MHz)