ZHCS927G May   2012  – January 2018 CDCM6208

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      简化电路原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information, Airflow = 0 LFM
    5. 6.5  Thermal Information, Airflow = 150 LFM
    6. 6.6  Thermal Information, Airflow = 250 LFM
    7. 6.7  Thermal Information, Airflow = 500 LFM
    8. 6.8  Single-Ended Input Characteristics (SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN, SYNCN, REF_SEL)
    9. 6.9  Single-Ended Input Characteristics (PRI_REF, SEC_REF)
    10. 6.10 Differential Input Characteristics (PRI_REF, SEC_REF)
    11. 6.11 Crystal Input Characteristics (SEC_REF)
    12. 6.12 Single-Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
    13. 6.13 PLL Characteristics
    14. 6.14 LVCMOS Output Characteristics
    15. 6.15 LVPECL (High-Swing CML) Output Characteristics
    16. 6.16 CML Output Characteristics
    17. 6.17 LVDS (Low-Power CML) Output Characteristics
    18. 6.18 HCSL Output Characteristics
    19. 6.19 Output Skew and Sync to Output Propagation Delay Characteristics
    20. 6.20 Device Individual Block Current Consumption
    21. 6.21 Worst Case Current Consumption
    22. 6.22 Timing Requirements, I2C Timing
    23. 6.23 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Typical Device Jitter
      2. 8.3.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 8.3.3  VCO Calibration
      4. 8.3.4  Reference Divider (R)
      5. 8.3.5  Input Divider (M)
      6. 8.3.6  Feedback Divider (N)
      7. 8.3.7  Prescaler Dividers (PS_A, PS_B)
      8. 8.3.8  Phase Frequency Detector (PFD)
      9. 8.3.9  Charge Pump (CP)
      10. 8.3.10 Fractional Output Divider Jitter Performance
      11. 8.3.11 Device Block-Level Description
      12. 8.3.12 Device Configuration Control
      13. 8.3.13 Configuring the RESETN Pin
      14. 8.3.14 Preventing False Output Frequencies in SPI/I2C Mode at Start-Up
      15. 8.3.15 Input MUX and Smart Input MUX
    4. 8.4 Device Functional Modes
      1. 8.4.1 Control Pins Definition
      2. 8.4.2 Loop Filter Recommendations for Pin Modes
      3. 8.4.3 Status Pins Definition
      4. 8.4.4 PLL Lock Detect
      5. 8.4.5 Interface and Control
        1. 8.4.5.1 Register File Reference Convention
        2. 8.4.5.2 SPI - Serial Peripheral Interface
          1. 8.4.5.2.1 Writing to the CDCM6208
          2. 8.4.5.2.2 Reading From the CDCM6208
          3. 8.4.5.2.3 Block Write/Read Operation
          4. 8.4.5.2.4 I2C Serial Interface
    5. 8.5 Programming
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures
        1. 9.2.2.1  Jitter Considerations in SERDES Systems
        2. 9.2.2.2  Jitter Considerations in ADC and DAC Systems
        3. 9.2.2.3  Configuring the PLL
        4. 9.2.2.4  Programmable Loop Filter
        5. 9.2.2.5  Loop filter Component Selection
        6. 9.2.2.6  Device Output Signaling
        7. 9.2.2.7  Integer Output Divider (IO)
        8. 9.2.2.8  Fractional Output Divider (FOD)
        9. 9.2.2.9  Output Synchronization
        10. 9.2.2.10 Output Mux on Y4 and Y5
        11. 9.2.2.11 Staggered CLK Output Power Up for Power Sequencing of a DSP
  10. 10Power Supply Recommendations
    1. 10.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 10.1.1 Mixing Supplies
      2. 10.1.2 Power-On Reset
      3. 10.1.3 Slow Power-Up Supply Ramp
      4. 10.1.4 Fast Power-Up Supply Ramp
      5. 10.1.5 Delaying VDD_Yx_Yy to Protect DSP IOs
    2. 10.2 Device Power-Up Timing
    3. 10.3 Power Down
    4. 10.4 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Reference Schematics
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.18 HCSL Output Characteristics

VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fOUT-I Output frequency Integer output divider V1 1.55 400 MHz
V2 1.91 400
fOUT-F Output frequency Fractional output divider 0.78 400 MHz
fACC-F Output frequency error(1) Fractional output divider –1 1 ppm
VCM Output common-mode voltage VDD_Yx_Yy = 2.5/3.3 V 0.2 0.34 0.55 V
VDD_Yx_Yy = 1.8 V 0.2 0.33 0.55 V
|VOD| Differential output voltage VDD_Yx_Yy = 2.5/3.3 V; 0.4 0.67 1 V
|VOD| Differential output voltage VDD_Yx_Yy = 1.8 V 0.4 0.65 1 V
VOUT Differential output peak-to-peak voltage VDD_Yx_Yy = 2.5/3.3 V 1 2.1 V
Differential output peak-to-peak voltage VDD_Yx_Yy = 1.8 V 2 ×
|V OD|		 V
tR/tF Output rise/fall time Measured from VDIFF= –100 mV to VDIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V 100 167 250 ps
tR/tF Output rise/fall time Measured from VDIFF= –100 mV to VDIFF= +100 mV, VDD_Yx_Yy = 1.8 V 120 192 295 ps
PN-floor Phase noise floor fOUT = 122.88 MHz VDD_Yx_Yy = 1.8 V –158.8 –153 dBc/Hz
VDD_Yx = 2.5/3.3 V –157.6 –153 dBc/Hz
ODC Output duty cycle Not in bypass mode 45% 55%
(1) The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach of a ½ 20multiple, the actual output frequency error is 0.
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