米6体育平台手机版

ZHCS927G May 2012 – January 2018 CDCM6208

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RGZ|48
- MPQF123F

散热焊盘机械数据 (封装 | 引脚)

RGZ|48
- QFND014T

订购信息

8.3.10 Fractional Output Divider Jitter Performance

The fractional output divider jitter performance is a function of the fraction output divider input frequency as well as actual fractional divide setting itself. To minimize the fractional output jitter, TI recommends using the least number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 30, the largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in the middle range of the fractional divider are selected.

CDCM6208 Fractional_divider_bit_jitter_300_SCAS931.png

Figure 30. Fractional Divider Bit Selection Impact on Jitter (f_FRAC = 300 MHz)

CDCM6208 Fractional_divider_bit_TJ_SCAS931.gif

Figure 32. Fractional Divider Bit Selection Impact on T_J (Typical)

CDCM6208 Fractional_divider_input_frequency_jitter_SCAS931.png

Figure 31. Fractional Divider Input Frequency Impact on Jitter (Using Divide by x.73 Example)

CDCM6208 Fractional_divider_bit_TJ_voltage_SCAS931.gif

Figure 33. Fractional Divider Bit Selection Impact on T_J
(Maximum Jitter Across Process, Voltage and Temperature)

Tested using a LeCroy 40 Gbps RealTime scope over a time window of 200 ms. The R_J impact on T_J is estimated for a BERT 10^(-12) – 1. This measurement result is overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.