ZHCS927G May 2012 – January 2018 CDCM6208
PRODUCTION DATA.
The CDCM6208 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider. Completing the CDCM6208 device are the combination of integer and fractional output dividers, and universal output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs than the digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the external power supply rail with a PSNR of better than –50 dB at all frequencies. The regulator capacitor pin REG_CAP should be connected to ground by a 10 µF capacitor with low ESR (for example, below 1-Ω ESR) to ensure stability.