ZHCS927G May 2012 – January 2018 CDCM6208
PRODUCTION DATA.
The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization of which vitals are mapped to these two pins. Table 12 lists the three events that can be mapped to each status pin and which can also be read in the register space.
| STATUS SIGNAL NAME | SIGNAL TYPE | SIGNAL NAME | REGISTER BIT NO. | DESCRIPTION |
|---|---|---|---|---|
| SEL_REF | LVCMOS | STATUS0, 1 | Reg 3.12
Reg 3.9 |
Indicates Reference Selected for PLL:
0 → Primary input selected to drive PLL 1 → Secondary input selected to drive PLL |
| LOS_REF | LVCMOS | STATUS0, 1 | Reg 3.11
Reg 3.8 |
Loss of selected reference input observed at active input:
0 → Reference input present 1 → Loss of reference input Important Note 1: For LOS_REF to operate properly, the secondary input SEC_IN must be enabled. Set register Q4.5=1. If register Q4.5 is set to zero, LOS_REF will output a static high signal regardless of the actual input signal status on PRI_IN. |
| PLL_UNLOCK | LVCMOS | STATUS0, 1 | Reg 3.10
Reg 3.7 |
Indicates unlock status for PLL (digital):
PLL locked → Q21.02 = 0 and VSTATUS0/1= VIH PLL unlocked → Q21.2 = 1 and VSTATUS0/1= VILSee note (1) Note 2: I f the smartmux is enabled and both reference clocks stall, the STATUSx output signal will 98% of the time indicate the LOS condition with a static high signal. However, in 2% of the cases, the LOS detection engine erroneously stalls at a state where the STATUSx output PLL lock indicator will signalize high for 511 out of every 512 PFD clock cycles. |
NOTE
It is recommended to assert only one out of the three register bits for each of the status pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference clock sources on STATUS1 output, the device register settings would be Q3.12 = Q3.7 = 1 and Q3.11 = Q3.10 = Q3.9 = Q3.8 = 0. If a status pin is unused, it is recommended to set the according 3 register bits to zero (for example, Q3[12:9] = 0 for STATUS0 = 0). If more than one bit is enabled for each STATUS signal, the function becomes OR'ed. For example, if Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if the device goes out of lock or the selected reference clock signal is lost.