9.2.2.2 Jitter Considerations in ADC and DAC Systems

A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity. The following test results were achieved connecting the CDCM6208 to ADC and DACs:

Figure 52. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49

Figure 53. IF = 60 MHz Fclk = 122.88 MHz CDCM6208 Driving ADC

Observation: Up to an IF = 100 MHz, the ADC performance when driven by the CDCM6208 (Figure 53) is similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering (Figure 52).

Conclusion: Therefore, the CDCM6208 is usable for applications up to 100 MHz IF. For IF above 100 MHz, the SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and other outputs running at different integer frequencies.

Figure 54. DAC Driven by Lab Source and CDCM6208 in Comparison (Performance Identical)

Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208 compared to driving the DAC with a perfect lab source. Therefore, the CDCM6208 provides sufficient low noise to drive a 245.76 MHz DAC.