9.2.2.3 Configuring the PLL

The CDCM6208 allows configuring the PLL to accommodate various input and output frequencies either through an I²C or SPI programming interface or in the absence of programming, the PLL can be configured through control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop Filter, Feedback Divider, Prescaler Divider, and Output Dividers.

For the PLL to operate in closed-loop mode, the following condition in Equation 1 has to be met when using primary input for the reference clock, and the condition in Equation 2 has to be met when using secondary input for the reference clock.

Equation 1.

Equation 2.

In Equation 1 and Equation 2, ƒ_{PRI_REF} is the reference input frequency on the primary input and ƒ_{SEC_REF} is the reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the feedback divider, and PS_A the prescaler divider A.

The output frequency, ƒ_OUT, is a function of ƒ_VCO, the prescaler A, and the output divider (O), and is given by Equation 3. (Use PS_B in for outputs 2, 3, 6, and 7).

Equation 3.

When the output frequency plan calls for the use of some output dividers as fractional values, the following steps are needed to calculate the closest achievable frequencies for those using fractional output dividers and the frequency errors (difference between the desired frequency and the closest achievable frequency).

• Based on system needs, decide the frequencies that need to have best possible jitter performance.
• Once decided, these frequencies need to be placed on integer output dividers.
• Then a frequency plan for these frequencies with strict jitter requirements can be worked out using the common divisor algorithm.
• Once the integer divider plans are worked out, the PLL settings (including VCO frequency, feedback divider, input divider and prescaler divider) can be worked out to map the input frequency to the frequency out of the prescaler divider.
• Then calculate the fractional divider values (whose values must be greater than 2) that are needed to support the output frequencies that are not part of the common frequency plan from the common divisor algorithm already worked out.
• For each fractional divider value, try to represent the fractional portion in a 20-bit binary scheme, where the first fractional bit is represented as 0.5, the second fractional bit is represented as 0.25, third fractional bit is represented as 0.125 and so on. Continue this process until the entire 20-bit fractional binary word is exhausted.
• Once exhausted, the fraction can be calculated as a cumulative sum of the fractional bit x fractional value of the fractional bit. Once this is done, the closest achievable output frequency can be calculated with the mathematical function of the frequency out of the prescaler divider divided by the achievable fractional divider.
• The frequency error can then be calculated as the difference between the desired frequency and the closest achievable frequency.