9.2.2.8 Fractional Output Divider (FOD)

The CDCM6208 incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non-integer output divide ratios of the PLL frequencies. This feature is useful when systems require different, unrelated frequencies. The fractional output divider architecture is shown in Figure 56.

Figure 56. Fractional Output Divider Principle Architecture (Simplified Graphic, not Showing Output Divider Bypass Options)

The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The fractional values available are all possible 20-b representations of fractions within the following range:

• 1.0 ≤ ƒrac_DIV ≤ 1.9375
• 2.0 ≤ ƒrac_DIV ≤ 3.875
• 4.0 ≤ ƒrac_DIV ≤ 5.875
• x.0 ≤ ƒrac_DIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254
• 254.0 ≤ ƒrac_DIV ≤ 255.875
• 256.0 ≤ ƒrac_DIV ≤ 256.99999

The CDCM6208 user GUI comprehends the fractional divider limitations; therefore, using the GUI to comprehend frequency planning is recommended.

The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from 50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths (approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (< 1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional divider enable bit, which engages the higher performing integer divider.