9.2.2.9 Output Synchronization

Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208, this signal comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output synchronization is to toggle the SYNCN pin. When SYNC is asserted (V_SYNCN ≤ V_IL), all outputs are disabled (high-impedance) and the output dividers are reset. When SYNC is de-asserted (V_SYNCN ≥ V_IH), the device first internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles. For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.

The SYNC feature is particularly helpful in systems with multiple CDCM6208. If SYNC is released simultaneously for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices configured to identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew uncertainty due to sync remains ±2 clock cycles.

Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values (PS_A=PS_B).

Figure 57. SYNCN to Output Delay Uncertainty