9.2.2.11 Staggered CLK Output Power Up for Power Sequencing of a DSP

DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term reliability problems, TI recommends avoiding any clock signal to the DSP until the DSP power rail is also powered up. This can be achieved in two ways using the CDCM6208:

1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on outputs one by one through serial interface after each DSP rail becomes powered up accordingly.
2. Output Power supply domain control: An even easier scheme might be to connect the clock output power supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208 output will remain disabled until the DSP rails ramps up as well. Figure 58 shows the turnon behavior.

Figure 58. Sequencing the Output Turnon Through Sequencing the Output Supplies
Output Y2 Powers Up While Output Y0 is Already Running