10.1.2 Power-On Reset

The CDCM6208 integrates a built-in POR circuit, that holds the device in power down until all input, digital, and PLL supplies have reached at least 1.06 V (minimum) to 1.24 V (maximum). After this power-on release, device internal counters start (see Device Power-Up Timing) followed by device calibration. While the device digital circuit resets properly at this supply voltage level, the device is not ready to calibrate at such a low voltage. Therefore, for slow power-up ramps, the counters expire before the supply voltage reaches the minimum voltage of 1.71 V. Hence for slow power-supply ramp rates, it is necessary to delay calibration further using the PDN input.