ZHCSEM4 February 2016 CSD95472Q5MC
PRODUCTION DATA.
5 Pin Configuration and Functions
Top View
Pin Functions
| PIN | DESCRIPTION | |
|---|---|---|
| NUMBER | NAME | |
| 1 | IOUT | Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current. |
| 2 | REFIN | External reference voltage input for current sensing amplifier. |
| 3 | ENABLE | Enables device operation. If ENABLE = logic HIGH, turns on device. If ENABLE = logic LOW, the device is turned off and both MOSFET gates are actively pulled low. An internal 100 kΩ pulldown resistor will pull the ENABLE pin LOW if left floating. |
| 4 | PGND | Power ground, connected directly to pin 13. |
| 5 | VDD | Supply voltage to gate driver and internal circuitry. |
| 6 | VSW | Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor. |
| 7 | VIN | Input voltage pin. Connect input capacitors close to this pin. |
| 8 | BOOT_R | Return path for HS gate driver, connected to VSW internally. |
| 9 | BOOT | Bootstrap capacitor connection. Connect a minimum of 0.1 µF 16 V X7R ceramic capacitor from BOOT to BOOT_R pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. |
| 10 | FCCM | This pin enables the diode emulation function. When this pin is held LOW, diode emulation mode is enabled for sync FET. When FCCM is HIGH, the device is operated in forced continuous conduction mode. An internal 5 µA current source will pull the FCCM pin to 3.3 V if left floating. |
| 11 | TAO/ FAULT |
Temperature Analog Output. Reports a voltage proportional to the die temperature. An ORing diode is integrated in the IC. When used in multiphase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown occurs. TAO should be bypassed to PGND with a 1 nF 16 V X7R ceramic capacitor. |
| 12 | PWM | Pulse width modulated tri-state input from external controller. Logic LOW sets control FET gate low and sync FET gate high. Logic HIGH sets control FET gate high and sync FET gate low. Open or High Z sets both MOSFET gates low if greater than the tri-state shutdown hold-off time (t3HT). |
| 13 | PGND | Power ground. |